Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Integrated circuit with clock generator

Abstract: A microprocessor or other integrated circuit including a clock generator circuit which is dependent on an externally-provided reference signal includes the capability of detecting the loss of this externally-provided reference signal and producing an alternate clock signal despite the loss of the reference. In a particular embodiment, the clock generator comprises a phase locked loop frequency synthesizer which normally relies on an external crystal oscillator for its reference frequency signal. The generator includes a circuit for detecting abnormalities in the crystal signal and switching the voltage controlled oscillator of the frequency synthesizer to an internally-generated reference voltage. In the particular embodiment, the clock generator is also capable of producing a reset signal in response to the loss of the reference signal.

Modified source/drain implants in a double-poly non-volatile memory process

Abstract: Implementing modified souce/drain implants in a non-volatile memory process while leaving the source/drain regions in the memory cells of the device unmodified and adding no critical mask steps. Methods for implementing both low dose drain and graded source/drain modifications in a double poly non-volatile memory process include the possibility of leaving the spacers used to modify the peripheral source/drain regions in place in the array portion of the device. Alternate methods include the possibility of removing the spacers in the array portion without the addition of critical mask steps and of keeping the spacers out of the array portion entirely.

Method of selecting a memory cell in a magnetic random access memory device

Abstract: Improved methods for selecting memory cells in magnetic random access memory (MRAM) are provided Whenever a state in a memory cell is sensed, a MRAM requires to adjust an output of comparator to a zero voltage (auto-zeroing step) before the content of memory cell is detected This invention sequentially accesses memory cells 29-30 once sense line 25 is selected and auto-zeroed Accordingly, a higher speed operation is attained because the invention does not require an auto-zeroing step every sensing a memory cell

Circuit and method of controlling mixer linearity

Abstract: An integrated receiver circuit (10) has a first amplifier (12) coupled for receiving a radio frequency (RFIN) input signal. A mixer (16) has an RF input coupled to an output of the first amplifier, a local oscillator (LO) input coupled for receiving an LO signal, and an output for providing an intermediate frequency (IF) signal. A second amplifier (20) has an input coupled for receiving the IF signal, and an output for providing a receive signal strength indicator (RSSI) signal representative of an input power level of the receiver signal path. A feedback circuit (22-26 or 72, 78) is coupled between the first output of the second amplifier and a linearity control input of the mixer for controlling linearity of the mixer.

Method for fabricating a semiconductor device using lateral gettering

Abstract: A semiconductor structure (20) includes a silicon layer (16) formed on an oxide layer (14) Gettering sinks (31, 32) are formed in the silicon layer (16) Lateral gettering is performed to effectively remove impurities from a first section (26) of the semiconductor layer (16) An insulated gate semiconductor device (40) is then formed in semiconductor layer (16), wherein a channel region (55) of the device (40) is formed in the first section (26) of the semiconductor layer (16) A gate dielectric layer (42) of the device (40) is formed over a portion of the first section (26) after the lateral gettering process, thereby enhancing the integrity of the gate dielectric layer (42)