Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Paged memory management unit which evaluates access permissions when creating translator

Abstract: A paged memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of descriptors comprising one or more translation tables stored in a memory, the PMMU assembling each of the logical addresses and the corresponding physical address into a respective translator. In general, the PMMU includes: a cache having a plurality of storage locations for storing the translators, each of the storage locations including a write protect indicator and a read protect indicator adapted to be selectively set; translation control logic for storing an assembled translator in a selected one of the storage locations, the translation control logic setting the write protect indicator of the one storage location in response to a write protect signal associated with the descriptor used to assemble the translator and the read protect indicator of the one storage location in response to a read protect signal associated with that descriptor; and access control logic for preventing the translator from being used to translate the logical address in support of a write operation if the write protect indicator of the one storage location is set or in support of a read operation if the read protect indicator of the one storage location is set. In the preferred form, the logical address has an access privilege level associated therewith and the descriptor includes a selected write access privilege level and a selected read access privilege level, the translation control logic setting the write protect indicator of the one storage location if the access privilege level associated with the logical address is logically less than the write access privilege level and the read protect indicator of the one storage location if the access privilege level associated with the logical address is logically less than the read access privilege level.

Voltage clamped differential to single ended converter circuit

Abstract: A MOS differential to single ended converter circuit is provided for supplying a single ouput signal in response to first and second differentially related current being supplied to first and second junctions thereof. The converter circuit includes first and second MOS transistors each having gate, drain and source electrodes with the gate electrodes being coupled together while the drain and gate electrodes of the first transistor are interconnected. The drain and source electrodes of the pair of transistors are respectively coupled in series with the first and second junctions. First and second bipolar transistors each having first, second and control electrodes are provided for limiting the voltage swing at the drain of the second MOS transistor. The contol and first electrodes of the first bipolar transistor are coupled respectively to the first and second junctions whiled the control and first electrodes of the second bipolar transistor are respectively coupled to the second and first junctions with the second electrodes of the two bipolar transistors being coupled to an additional common terminal.

Method of forming semiconductor device including interconnect barrier layers

Abstract: An interconnect overlies a semiconductor device substrate ( 10 ). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer ( 92 ) overlies the conductive barrier layer and the passivation layer ( 92 ) has an opening that exposes portions of the conductive barrier layer ( 82 ). In an alternate embodiment a passivation layer ( 22 ) overlies the interconnect, the passivation layer ( 22 ) has an opening ( 24 ) that exposes the interconnect and a conductive barrier layer ( 32 ) overlies the interconnect within the opening ( 24 ).

Electronic assembly having a double-sided leadless component

Abstract: An electronic assembly has a double-sided leadless component (10) and one or more printed circuit boards (30, 32). The component has a plurality of electrical terminations or pads (18) on both opposing major surfaces. Each of the printed circuit boards has a printed circuit pattern that has a plurality of pads (34, 36) that correspond to the electrical terminations on both sides of the double-sided leadless component. The electrical terminals on one side of the component are attached to the pads on the first substrate and the electrical terminals on the other side of the leadless component are attached to the pads on the second substrate. The printed circuit boards are joined together to form a multilayered circuit board (44) so that the double-sided leadless component is buried or recessed inside. The component is attached to the pads of the printed circuit board using solder.

Method of forming a split gate memory device and apparatus

Abstract: A split-gate memory device has a select gate having a first work function overlying a first portion of a substrate. A control gate having a second work function overlies a second portion of the substrate proximate the first portion. When the majority carriers of the split-gate memory device are electrons, the first work function is greater than the second work function. When the majority carriers of the split-gate memory device are holes, the first work function is less than the second work function. First and second current electrodes in the substrate are separated by a channel that underlies the control gate and select gate. The differing work functions of the control gate and the select gate result in differing threshold voltages for each gate to optimize device performance. For an N-channel device, the select gate is P conductivity and the control gate is N conductivity.