Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing

Abstract: A method for semiconductor wafer scribing utilizing perforated metal areas in the scribe regions. In one form, a method for fabricating a semiconductor device includes forming a plurality of semiconductor die (12) on a semiconductor wafer (10) such that the die are separated from one another by scribe regions (13). A test structure (14) is formed within one of the scribe regions and includes a perforated probe pad (16). In one embodiment, the probe pad is perforated by a plurality of slots (18). The perforations in the probe pad aid in scribing the semiconductor wafer by preventing metal lift-off which often occurs when cutting metal areas.

Complementary zener triggered bipolar esd protection

Abstract: An electrostatic discharge (ESD) protection clamp ( 61 ) for I/O terminals ( 22, 23 ) of integrated circuits (ICs) ( 24 ) comprises an NPN bipolar transistor ( 25 ) coupled to an integrated Zener diode ( 30 ). Variations in the break-down current-voltage characteristics ( 311, 312, 313, 314 ) of multiple prior art ESD clamps ( 31 ) in different parts of the same IC chip is avoided by forming the anode ( 301 ) of the Zener ( 30 ) in the shape of a base-coupled P+ annular ring ( 75 ) surrounded by a spaced-apart N+ annular collector ring ( 70 ) for the cathode ( 302 ) of the Zener ( 30 ). Even though an angled implant ( 51, 86, 98 ) used to form the N+ annular collector ring ( 70 ) causes location dependent variations in the width ( 531, 532 ) of the Zener space charge (ZSC) region ( 691, 692 ), the improved annular shaped clamp ( 61 ) always has a portion that initiates break-down at the design voltage so that variations in the width ( 531, 532 ) of the ZSC region ( 691, 692 ) do not cause significant variations in the clamp's current-voltage characteristics ( 611, 612, 613, 614 ).

Method and apparatus for interleaving data in an asymmetric digital subscriber line (ADSL) transmitter

Abstract: In an ADSL transmitter (62), data is flamed and split between a fast path and an interleave path by multiplexer (66) Data is forward error correction encoded in FEC encoder (70) Data on the interleave path is interleaved by interleaver (72) if an interleave depth (D) is >2 During interleaving, at least one additional read operation is performed, after a series of consecutive write and read operations The additional read operation permits interleaving to continue without waiting for a next frame of data to arrive at the interleaver An equal number of additional write operations compensates for the additional reads at a later point Use of an interleaving memory can also be avoided by turning off or disabling the interleaver, while still permitting data to be sent along the interleave path Transmit path controller (74) senses if D=1, and if so disables the interleaver and avoids the need for interleaver memory (64)

1- $\mu\hbox{m}$ Enhancement Mode GaAs N-Channel MOSFETs With Transconductance Exceeding 250 mS/mm

Abstract: In this letter, 1-mum GaAs-based enhancement-mode n-channel devices with channel mobility of 5500 cm2/Vmiddots and g m exceeding 250 mS/mm have been fabricated. The measured device parameters including threshold voltage Vth, maximum extrinsic transconductance gm, saturation current Idss , on-resistance Ron, and gate current are 0.11 V, 254 mS/mm, 380 mA/mm, 4.5 Omegamiddotmm, and < 56 pA for a first wafer and 0.08 V, 229 mS/mm, 443 mA/mm, 4.5 Omegamiddotmm, and < 90 pA for a second wafer, respectively. With an intrinsic transconductance gmi of 434 mS/mm, GaAs enhancement-mode MOSFETs have reached expected intrinsic device performance

Semiconductor package having optimized wire bond positioning

Abstract: Closely-spaced bonding wires may be used in a variety of different packaging applications to achieve improved electrical performance. In one embodiment, two adjacent bonding wires within a wire grouping are closely-spaced if a separation distance D between the two adjacent wires is met for at least 50 percent of the length of the shorter of the two adjacent wires. In one embodiment, the separation distance D is at most two times a diameter of the wire having the larger diameter of the two adjacent wires. In another embodiment, the separation distance D is at most three times a wire-to-wire pitch between the two adjacent wires. Each wire grouping may include two of more closely-spaced wires. Wire groupings of closely-spaced bonding wires may be used to form, for example, power-signal-ground triplets, signal-ground pairs, signal-power pairs, or differential signal pairs or triplets.