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Institution

Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..


Papers
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Patent
02 Jul 1990
TL;DR: Selective planarization as discussed by the authors is a method for fabricating a multi-layer semiconductor device using a photoresist mask patterning and developed to form a window which exposes an area between the conductive members.
Abstract: The disclosed invention is a method for fabricating a multi-layer semiconductor device using selective planarization. In accordance with one embodiment of the invention, conductive members are formed on a substrate and a first insulating layer is deposited onto the substrate and the conductive members. A second insulating layer, which has a lower flow temperature than the flow temperature of the first layer, is deposited onto the first layer. A photoresist mask is patterned and developed to form a window which exposes an area between the conductive members. The device is preferentially etched such that only the exposed areas of the second insulating layer are removed, leaving the first insulating layer intact. An anisotropic etch is used to remove portions of the first insulating layer, leaving spacers along the edges of the conductive members. The photoresist mask is removed and a heating step is performed which flows the remaining portions of the second insulating layer, but not the first layer. Since the second insulating material remains in only selective areas, the process is termed selective planarization. The method provides the benefit that areas which are to be etched to form contact hole or vias are not planarized, unlike existing blanket planarization methods, and a self-aligned contact is formed between the conductive members to the substrate.

52 citations

Patent
30 Aug 2006
TL;DR: In this paper, a thermal detection device coupleable to the output of the current source circuit is used to detect the voltage difference between the voltage at the thermal detector in response to the second current and the voltage measured by the voltage detector at the first current.
Abstract: A device includes a current source circuit to separately provide a first current and a second current and a thermal detection device coupleable to the output of the current source circuit. The device further includes a voltage detection circuit to provide a first indicator of a first voltage representative of a voltage at the thermal detection device in response to the second current and a second indicator of a second voltage representative of a voltage difference between the voltage at the thermal detection device in response to the second current and a voltage at the voltage detection device in response to the first current. The device further includes a temperature detection circuit to provide an over-temperature indicator based on the first indicator and the second indicator, wherein an operation of a circuit component of the device can be adjusted based on the over-temperature indicator.

52 citations

Patent
03 Jun 1998
TL;DR: In this paper, a bus request mechanism in each of the processors dynamically calculates normalized priority values based on relative needs across the system, where the normalized priority calculation is based on monitoring the fullness of memory segments of the shared memory associated with each processor.
Abstract: An arbitration and task switching technique in a real-time multiprocessor data processing system (20) having a common bus (32) and a segmented shared memory (30), where fullness of memory segments of the shared memory (30) is used as a measurement for arbitration and task switching priorities. A bus request mechanism in each of the processors dynamically calculates normalized priority values based on relative needs across the system (20). The normalized priority calculation is based on monitoring the fullness of memory segments of the shared memory (30) associated with each processor (24, 26, 28) of the system (20). Using this normalized priority calculation, the bus access order and bus bandwidth are optimally allocated according to tasks executed by the processors (24, 26, 28). Also, the normalized priority calculation and a preprogrammed threshold is used to control task switching in the multi-processor system (20).

52 citations

Journal ArticleDOI
TL;DR: A new technique, called statistical neuro-space mapping, is proposed for large-signal statistical modeling of nonlinear microwave devices, which uses nonlinear mapping to overcome the accuracy limitations of the linear mapping in modeling large statistical variations among different devices.
Abstract: A new technique, called statistical neuro-space mapping, is proposed for large-signal statistical modeling of nonlinear microwave devices. The proposed technique is an advance over a recent linear statistical mapping technique. It uses nonlinear mapping to overcome the accuracy limitations of the linear mapping in modeling large statistical variations among different devices. For a given population of device samples, the nominal device model is determined from dc, small-, and large-signal data. The behavior of a random device in the population is obtained by a nonlinear mapping from that of the nominal device. The unknown mapping function is represented by neural networks trained using dc and small-signal data of various devices in the population. A novel statistical mapping is formulated by introducing a compact set of statistical variables to control the mapping to map from the nominal device toward different devices in the population. A new training method is proposed for simultaneous statistical parameter extraction and neural-network training. The proposed technique is confirmed by statistical modeling of microwave transistor examples, and use of the models in statistical analyses of a two-stage amplifier. It is demonstrated that, for small or large statistical variations, the proposed technique outperforms the existing methods, using a minimum amount of expensive large-signal data to provide the most accurate large-signal statistical model.

52 citations

Patent
19 Dec 2002
TL;DR: In this article, a wafer inspection image is provided and the coordinates of potential defects in the wafer are determined using CAD data, and the CAD coordinates are then used to navigate through the reticle for the Wafer in order to locate reticle defects corresponding to the detected wafer defects.
Abstract: Systems and methods are described for translating detected wafer defect coordinates to reticle coordinates using CAD data. A wafer inspection image is provided and coordinates of potential defects in the wafer are determined. Then the wafer inspection image is converted into a predetermined image format. CAD data for the device under test is then used to produce a second image, also in the predetermined image format. The CAD-derived image and the wafer-derived image are then aligned, and the coordinates of potential defects in the wafer are converted into CAD coordinates. The CAD coordinates are then used to navigate through the reticle for the wafer in order to locate reticle defects corresponding to the detected wafer defects.

52 citations


Authors

Showing all 7673 results

NameH-indexPapersCitations
David Blaauw8775029855
Krishnendu Chakrabarty7999627583
Rajesh Gupta7893624158
Philippe Renaud7777326868
Min Zhao7154724549
Gary L. Miller6330613010
Paul S. Ho6047513444
Ravi Subrahmanyan5935314244
Jing Shi5322210098
A. Alec Talin5231112981
Chi Hou Chan485119504
Lin Shao4838012737
Johan Åkerman483069814
Philip J. Tobin471866502
Alexander A. Demkov473317926
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20211
20203
201910
201826
201779
2016267