Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Portable electronic device with removable display

Abstract: A portable electronic device including a display detachably mounted to a power source. The display including a virtual image display apparatus. The power source including a detachably mounted battery. A communication interface is provided between the display apparatus and the portable electronic device for permitting data exchange between the display apparatus and the portable electronic device. The communication interface provided can be either a standard electrical interface such as an electrical connector or a solid form factor design including cooperating contact areas or a wireless interface such as an infra red optical link or a radio frequency link.

Method of forming an electrical interconnect

Abstract: Interconnect bumps are formed on a circuit substrate using printing or dispensing techniques with a wet photoresist layer as a mask. A conductive paste is disposed in openings of a wet photoresist layer. The conductive paste is at least partially cured before the wet photoresist layer is removed. Alternatively, the wet photoresist layer may remain if it is a photo-imagable polyimide.

Memory Redundancy to Replace Addresses with Multiple Errors

Abstract: A method and apparatus are provided for error correction of a memory by using a first memory ( 18 ), second memory ( 14 ), and redundant memory ( 19 ) to perform error correction code (ECC) processing on data retrieved from the first memory ( 18 ) by using the redundant memory ( 19 ) to replace entries in the second memory ( 14 ) having repeat addresses, thereby freeing entries in the second memory ( 14 ) for use in detecting and managing errors identified by the ECC processing.

Floating point multiplier/accumulator with reduced latency and method thereof

Abstract: A circuit (10) for multiplying two floating point operands (A and C) while adding or subtracting a third floating point operand (B) removes latency associated with normalization and rounding from a critical speed path for dependent calculations. An intermediate representation of a product and a third operand are selectively shifted to facilitate use of prior unnormalized dependent resultants. Logic circuitry (24, 42) implements a truth table for determining when and how much shifting should be made to intermediate values based upon a resultant of a previous calculation, upon exponents of current operands and an exponent of a previous resultant operand. Normalization and rounding may be subsequently implemented, but at a time when a new cycle operation is not dependent on such operations even if data dependencies exist.

Instruction accelerator for processing loop instructions with address generator using multiple stored increment values

Abstract: An instruction accelerator which includes an instruction source, and a single instruction multiple data array processor which executes the instructions supplied by the instruction source. A loop processor identifies all loop type instructions which are supplied by the instruction source, copies those instructions supplied by the instruction source into a loop memory, and supplies those loop instructions to the single instruction multiple data array processor in the order received, at the rate required by the single instruction multiple data array processor, and as many times as required by the loop count field.