Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology

Abstract: In a general case of 3D integrated circuit (IC) technology, it is desirable to design a die for 3D integration with flexibility to facilitate integration with a number of other circuit dies. We present a generic circuit technique which minimizes power consumption and circuit area while allowing reliable signal transfer between 3D dies as well as enabling the design of a bonded interface circuitry without a complete knowledge of inter-strata connection configurations. We also present parasitic RC characteristics of inter-strata connection elements, such as micro-bumps and through-substrate vias, and discuss the technology scaling trends. An inter-strata signal transmission, according to our method, has receive and transmit circuitry with programmable power supply which can be independently controlled for achieving optimum power and signal drive. In addition, the receive circuitry includes hysteresis to allow superior signal integrity in the presence of inter-strata parasitic variations

Process for forming an electronic device including a transistor having a metal gate electrode

Abstract: An electronic device includes an n-channel transistor and a p-channel transistor. The p-channel transistor has a first gate electrode with a first work function and a first channel region including a semiconductor layer immediately adjacent to a semiconductor substrate. In one embodiment, the first work function is less than the valence band of the semiconductor layer. In another embodiment, the n-channel transistor has a second gate electrode with a second work function different from the first work function and closer to a conduction band than a valence band of a second channel region. A process of forming the electronic device includes forming first and second gate electrodes having first and second work functions, respectively. First and second channel regions having a same minority carrier type are associated with the first and second gate electrodes, respectively.

Integrated circuit memory using fusible links in a scan chain

Abstract: An integrated circuit memory (140) includes programmable fuses (20) coupled to scannable flip-flops (25). The programmable fuses (20) and scannable flip-flops (25) are implemented in a scan chain, and are used to program specific information about the integrated circuit memory (140), such as for example, repair (redundancy) information, wafer lot number and wafer number, die position on the wafer, or any other information that would be useful during or after package testing.

Handover based on a quality of service metric obtained from a mac layer of a received signal

Abstract: A wireless communication unit (132) comprises a receiver operably coupled to a signal processing function arranged to make a hand-over determination based on a communication signal received from a serving communication station. The signal processing function is arranged to perform a hand-over operation based on at least one quality of service metric(s) obtained from a medium access control (MAC) layer of a received signal. The embodiments comprise identifying an optimal hand-over candidate that enables a more effective hand-over from a first WLAN to a second WLAN or a cellular system.

Multi-layer source/drain stressor

Abstract: A method for forming a semiconductor device (10) includes forming a recess (26) in a source region and a recess (28) in a drain region of the semiconductor device. The method further includes forming a first semiconductor material layer (32) in the recess (26) in the source region and a second semiconductor material layer (34) in the recess (28) in the drain region, wherein each of the first semiconductor material layer (32) and the second semiconductor material layer (38) are formed using a stressor material having a first ratio of an atomic concentration of a first element and an atomic concentration of a second element, wherein the first element is silicon and a first level of concentration of a doping material. The method further includes forming additional semiconductor material layers (36, 38, 40, 42) overlying the first semiconductor material layer (32) and the second semiconductor material layer (34) that have a different ratio of the atomic concentration of the first element and the second element.