Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Ultra wide bandwidth communications method and system

Abstract: An ultra wide bandwidth, high speed, spread spectrum communications system uses short wavelets of electromagnetic energy to transmit information through objects such as walls or earth. The communication system uses baseband codes formed from time shifted and inverted wavelets to encode data on a RF signal. Typical wavelet pulse durations are on the order of 100 to 1000 picoseconds with a bandwidth of approximately 8 GHz to 1 GHz, respectively. The combination of short duration wavelets and encoding techniques are used to spread the signal energy over a an ultra wide frequency band such that the energy is not concentrated in any particular narrow band (e.g. VHF: 30-300 MHz or UHF: 300-1000 MHz) and is not detected by conventional narrow band receivers so it does not interfere with those communication systems. The use of pulse codes composed of time shifted and inverted wavelets gives the system according to the present invention has a spatial resolution on the order of 1 foot which is sufficient to minimize the negative effects of multipath interference and permit time domain rake processing.

Optimal resource allocation in the OFDMA downlink with imperfect channel knowledge

Abstract: Previous research efforts on OFDMA resource allocation have typically assumed the availability of perfect channel state information (CSI). Unfortunately, this is unrealistic, primarily due to channel estimation errors, and more importantly, channel feedback delay. In this paper, we develop optimal resource allocation algorithms for the OFDMA downlink assuming the availability of only partial (imperfect) CSI. We consider both continuous and discrete ergodic weighted sum rate maximization subject to total power constraints, and average bit error rate constraints for the discrete rate case. We approach these problems using a dual optimization framework, allowing us to solve these problems with O(MK) complexity per symbol for an OFDMA system with K used subcarriers and M active users, while achieving relative optimality gaps of less than 10-5 for continuous rates and less than 10-3 for discrete rates in simulations based on realistic parameters.

A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers

Abstract: A 4-Mb toggle MRAM, built in 0.18-/spl mu/m five level metal CMOS technology, uses a 1.55 /spl mu/m/sup 2/ bit cell with a single toggling magneto tunnel junction to achieve a chip size of 4.5 mm /spl times/ 6.3 mm. The memory uses unidirectional programming currents controlled by locally mirrored write drivers to apply a robust toggle write sequence. An isolated read architecture driven by a balanced three input current mirror sense amplifier supports 25-ns cycle time asynchronous operation.

Smart/active RFID tag for use in a WPAN

Abstract: A system and method is provided for processing communication signals in a wireless personal area network (WPAN) using a transceiver comprising a first transmitter and a first receiver operable to transmit and receive signals using a first transmission protocol and a second transmitter operable to transmit signals using a second transmission protocol. In various embodiments, the first receiver is used to receive a first signal that was transmitted using the first communication protocol and the second transmitter is used to transmit a second signal using the second transmission protocol in response to receipt of the first signal. The second signal is then processed to determine the location of the object. In some embodiments, the first transmission protocol is compliant with an Institute of Electrical and Electronics Engineers 802.15.4 transmission protocol and the second transmission protocol is compliant with an Ultra-Wide Band (UWB) protocol.

A ZVS Interleaved Boost AC/DC Converter Used in Plug-in Electric Vehicles

Abstract: This paper presents a novel, yet simple zero-voltage switching (ZVS) interleaved boost power factor correction (PFC) ac/dc converter used to charge the traction battery of an electric vehicle from the utility mains. The proposed opology consists of a passive auxiliary circuit, placed between two phases of the interleaved front-end boost PFC converter, which provides enough current to charge and discharge the MOSFETs' output capacitors during turn-ON times. Therefore, the MOSFETs are turned ON at zero voltage. The proposed converter maintains ZVS for the universal input voltage (85 to 265 Vrms), which includes a very wide range of duty ratios (0.07-1). In addition, the control system optimizes the amount of reactive current required to guarantee ZVS during the line cycle for different load conditions. This optimization is crucial in this application since the converter may work at very light loads for a long period of time. Experimental results from a 3 kW ac/dc converter are presented in the paper to evaluate the performance of the proposed converter. The results show a considerable increase in efficiency and superior performance of the proposed converter compared to the conventional hard-switched interleaved boost PFC converter.