Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Defect Passivation With Fluorine and Interface Engineering for Hf-Based High- $k$ /Metal Gate Stack Device Reliability and Performance Enhancement

Abstract: Using a fluorinated high-fc/metal gate stack combined with a stress relieved preoxide (SRPO) pretreatment before high-fc deposition, we show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem, and performance degradation for high-fc is a concern. The novel fluorinated TaxCy/HfZrOx/SRPO gate stack device exceeds the positive-bias-temperature-instability and negative-bias-temperature-instability targets with sufficient margin and has electron mobility at 1 MV/cm comparable to the industrial high-quality polySi/SiON device on bulk silicon.

Automatic exposure control system for a digital camera

Abstract: An Automatic Exposure Control (AEC) regulates the operation of the digital camera sensor array. The acquisition of images and videos is optimized through having the automatic exposure control lock the exposure time of the photo-sensor array prior to performing any digital processing on the acquired image. The automatic exposure control determines the amount of exposure through moving the median brightness to the center of the dynamic range.

Semiconductor fabrication process using etch stop layer to optimize formation of source/drain stressor

Abstract: A semiconductor fabrication process includes forming an etch stop layer (ESL) (109) overlying a buried oxide (BOX) layer (102) and an active semiconductor layer (105) overlying the ESL. A gate electrode (112) is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors (130) are formed on the ESL where the source/drain stressors strain the transistor channel (115). Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.

Method for fabricating a semiconductor structure with reduced leakage current density

Abstract: A method for fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12); forming an interface including a seed layer (18) adjacent to the surface (12) of the silicon substrate (10), forming a buffer layer (20) utilizing molecular oxygen; and forming one or more layers of a high dielectric constant oxide (22) on the buffer layer (20) utilizing activated oxygen.

Dual surface SOI by lateral epitaxial overgrowth

Abstract: A semiconductor process and apparatus provide a planarized hybrid substrate (18) by exposing a buried oxide layer (80) in a first area (99), selectively etching the buried oxide layer (80) to expose a first semiconductor layer (70) in a second smaller seed area (98), and then epitaxially growing a first epitaxial semiconductor material from the seed area (98) of the first semiconductor layer (70) that fills the second trench opening (100) and grows laterally over the exposed insulator layer (80) to fill at least part of the first trench opening (99), thereby forming a first epitaxial semiconductor layer (101) that is electrically isolated from the second semiconductor layer (90). By forming a first SOI transistor device (160) over a first SOI layer (90) using deposited (100) silicon and forming first SOI transistor (161) over an epitaxially grown (110) silicon layer (101), a high performance CMOS device is obtained.