Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Method and apparatus for performing power on reset initialization in a data processing system

Abstract: A method and apparatus for performing power on reset initialization in a data processing system (40). In one form, the present invention uses a circuit (71) to ensure that a node (65) always power up to the correct logic level. This node (65) can then be used to initialize a latch (83) so that the latch (83) always drives a predetermined logic level at its data output when the latch (83) powers up. The data output of latch (83) is a Power On Reset signal which is asserted during power on reset initialization and which is negated when power on reset initialization is completed.

Phase locked loop using digital loop filter and digitally controlled oscillator

Abstract: A phase locked loop (10) with a phase detector (11), a digital loop filter (12), a digital controlled oscillator (13) and a divide-by-N circuit (14) generates a periodic signal which has a predetermined phase and voltage related to a reference clock signal. A phase and frequency detector (21) outputs an average of error between a feedback delay clock and a reference clock to the digital loop filter (12). The digital loop filter (12) processes the phase detector (11) output and the inband quantization noise utilizing a sigma delta converter. The digital loop filter (12) utilizes a non binary weight scheme to minimize the number of bits changing states. The digital controlled oscillator (13) generates a loop clock signal utilizing a plurality of digital programmable delay elements. A divide-by-N circuit (14) performs a divide by 2560.

Memory having negative voltage write assist circuit and method therefor

Abstract: A method of writing data to a selected column of a memory (10) includes selecting a first column. The data writing is initiated by applying a logic high to a first bit line (BL0) of the first column and a first potential to a second bit line (BLB0) of the first column that is lower than the logic high. The first potential is removed and a second potential is applied to the second bit line. The second potential is less than the first potential. The first potential may be ground (VSS), and the second potential may be a negative voltage (VNEG). Reducing the write voltage for the bit line that is receiving a logic low improves its ability to be written. By first bringing the logic low to the first potential, which may be ground, and then further reducing the applied voltage, the requirements on the source of the second potential are reduced.

Removable sidewall spacer for lightly doped drain formation using two mask levels

Abstract: A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDS) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Conformal materials such as CVD polysilicon may also be employed for this purpose. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implantation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation.

Semiconductor devices employing poly-filled trenches

Abstract: Structure and method are provided for semiconductor devices. The devices include trenches filled with highly doped polycrystalline semiconductor, extending from the surface into the body of the device for, among other things: (i) reducing substrate current injection, (ii) reducing ON-resistance and/or (iii) reducing thermal impedance to the substrate. For isolated LDMOS devices, the resistance between the lateral isolation wall (tied to the source) and the buried layer is reduced, thereby reducing substrate injection current. When placed in the drain of a lateral device or in the collector of a vertical device, the poly-filled trench effectively enlarges the drain or collector region, thereby lowering the ON-resistance. For devices formed on an oxide isolation layer, the poly-filled trench desirably penetrates this isolation layer thereby improving thermal conduction from the active regions to the substrate. The poly filled trenches are conveniently formed by etch and refill. Significant area savings are also achieved.