Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

An interface circuit for interfacing between asynchronous data in start/stop format and synchronous data

Abstract: A data interface circuit (33) for interfacing between an asynchronous data source providing data in start/stop format and a synchronous data communication channel (34, 35). The data interface circuit (33) has a transmit portion (41) and a receive portion (42) which function independently. Upon receipt of asynchronous data, the transmit portion (41) strips start and stop bits from the data and transmits the data in data frames of variable length chararcterized by beginning and ending with synchronizing idle codes. The synchronizing idle codes are transmitted in the absence of data to maintain synchronization. A code circuit (71) insures that a data word is never the same as the idle code. Similarly, upon receipt of synchronous data and idle codes, the receive portion (42) stores the data and controllably adds start and stop bits. Data in start/stop format is asynchronously provided at an output of the receive portion (42).

Threshold voltage and bulk inversion effects in nonclassical CMOS devices with undoped ultra-thin bodies

Abstract: Novel, or nonclassical effects due to carrier distribution in double-gate (DG) CMOS devices (e.g., FinFETs) with undoped ultra-thin silicon bodies (UTBs) are analyzed and modeled. The classical analysis of gate–gate charge coupling and threshold voltage (Vt) of fully depleted SOI MOSFETs by Lim and Fossum [Lim H-K, Fossum JG. Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFETs. IEEE Trans Electron Dev 1983;ED-30(October):1244–51.] is generalized to account for bulk inversion in UTBs, carrier-energy quantization, and short-channel effects (SCEs). The generalized charge coupling model physically and generically characterizes Vt for arbitrary gate biases, and explains an enhanced coupling in independent-gate (IG) FinFETs associated with bulk inversion. The impact of the carrier distribution on SCEs is also discussed. The effect on Vt of sparse, random dopants in the UTB is shown to be insignificant. Finally, bulk inversion is noted to prevail in strong inversion, where its net effect on device performance is beneficial.

Low rc product transistors in soi semiconductor process

Abstract: A semiconductor fabrication process includes forming a transistor gate overlying an SOI wafer having a semiconductor top layer over a buried oxide layer (BOX) over a semiconductor substrate. Source/drain trenches, disposed on either side of the gate, are etched into the BOX layer. Source/drain structures are formed within the trenches. A depth of the source/drain structures is greater than the thickness of the top silicon layer and an upper surface of the source/drain structures coincides approximately with the transistor channel whereby vertical overlap between the source/drain structures and the gate is negligible. The trenches preferably extend through the BOX layer to expose a portion of the silicon substrate. The source/drain structures are preferably formed epitaxially and possibly in two stages including an oxygen rich stage and an oxygen free stage. A thermally anneal between the two epitaxial stages will form an isolation dielectric between the source/drain structure and the substrate.

Secure provisioning in an untrusted environment

Abstract: Embodiments include methods for securely provisioning copies of an electronic circuit. A first entity (e.g., a chip manufacturer) embeds one or more secret values into copies of the electronic circuit. A second entity (e.g., an OEM): 1) embeds a trust anchor in a first copy of the electronic circuit; 2) causes the electronic circuit to generate a message signing key pair using the trust anchor and the embedded secret value(s); 3) signs provisioning code using a code signing private key; and 4) sends a corresponding code signing public key, the trust anchor, and the signed provisioning code to a third entity (e.g., a product manufacturer). The third entity embeds the trust anchor in a second copy of the electronic circuit and causes the electronic circuit to: 1) generate the message signing private key; 2) verify the signature of the signed provisioning code using the code signing public key; and 3) launch the provisioning code on the electronic circuit. The electronic circuit can authenticate itself to the OEM using the message signing key pair.

Solder plate reflow method for forming a solder bump on a circuit trace intersection

Abstract: A method for forming a solder-bumped circuit trace on a planar dielectric substrate includes fabricating a trace having an intersection between linear section, depositing onto the trace a uniform thin plate of solder alloy and reflowing the solder alloy to form a bump at the intersection. More particularly, the trace comprises first and second linear sections that intersect at an angle between 45 degrees and 135 degrees and have widths preferably between 50 and 150 microns. The solder plate is deposited, preferably by electroplating, at a thickness between about 10 and 25 microns. Thereafter, when the trace is heated to melt the solder layer, the solder coalesces at the intersection to form the bump.