Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Envelope-domain time series (ET) behavioral model of a Doherty RF power amplifier for system design

Abstract: In this paper, we present an envelope-domain behavioral model of a high-power RF amplifier. In this modeling approach, we use the signal envelope information, and the behavioral model is generated using an established nonlinear time-series approach to create a time-domain model that operates in the envelope or signal domain. We have generated a model of a 200-W Doherty amplifier from measured IQ data taken using a wideband code-division multiple-access excitation; the amplifier was driven from the linear regime into saturation. The time-series model was created using a time-delay embedding identified from auto-mutual information analysis, and an artificial neural network was used to fit the multivariate transfer function. The model has been validated using measured and simulated data, and it has been used in the development of a system-level design of a digital pre-distorter

Process for making a multilayer metallization structure

Abstract: A method for forming a via contact for devices having multilayer metallization is provided wherein a sacrificial layer is formed over a bottom interconnect layer, and an interlayer dielectric is formed on the sacrificial layer. A via is etched in the interlayer dielectric, exposing the sacrificial layer. The sacrificial layer is isotropically etched to expose an area of the interconnect metal that is larger than the area of the via and a via metallization is selectively formed on the interconnect metal by chemical vapor deposition so that the via, including a void created by the isotropic etch of the sacrificial layer, is filled with the via metallization, thereby providing a contact area to the bottom interconnect metal which is larger than the via metallization itself.

Multiple axis transducer with multiple sensing range capability

Abstract: A transducer package 20 includes a substrate 32 having a first axis of symmetry 36 and a second axis of symmetry 38 arranged orthogonal to the first axis of symmetry 36 . At least a first sensor 50 and a second sensor 52 each of which are symmetrically arranged on the substrate 32 relative to one of the first and second axes of symmetry 36 and 38 .The first and second sensors 50 and 52 are adapted to detect movement parallel to the other of the first and second axes of symmetry 36 and 38 . The first sensor 50 is adapted to detect movement over a first sensing range and the second sensor 52 is adapted to detect movement over a second sensing range, the second sensing range differing from the first sensing range.

Dynamic voltage adjustment for memory

Abstract: A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.

Method and means for controlling movement of a chuck in a test apparatus

Abstract: A sense circuit (23) for generating an actuating signal and a method of using the actuating signal to control movement of a wafer chuck (12). The sense circuit (23) has sense input terminals (24, 28) coupled to corresponding probe-card probes (19, 18). A wafer (26) having contact pads (42, 42') is mounted on the wafer chuck (12) and moved towards the probe-card probes (18, 19). When the probe-card probes (18, 19) contact corresponding contact pads (42', 42) on the wafer, the sense circuit (23) generates an actuating signal. The actuating signal, which is generated in accordance with the heights of the contact pads (42', 42), enables control circuit (48) of the prober (11). The control circuit limits the movement of the wafer chuck (12) to prevent damage to the probe card (12) or the wafer (26).