Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

A Predictive Performance Model for Superscalar Processors

Abstract: Designing and optimizing high performance microprocessors is an increasingly difficult task due to the size and complexity of the processor design space, high cost of detailed simulation and several constraints that a processor design must satisfy. In this paper, we propose the use of empirical non-linear modeling techniques to assist processor architects in making design decisions and resolving complex trade-offs. We propose a procedure for building accurate non-linear models that consists of the following steps: (i) selection of a small set of representative design points spread across processor design space using latin hypercube sampling, (ii) obtaining performance measures at the selected design points using detailed simulation, (iii) building non-linear models for performance using the function approximation capabilities of radial basis function networks, and (iv) validating the models using an independently and randomly generated set of design points. We evaluate our model building procedure by constructing non-linear performance models for programs from the SPEC CPU2000 benchmark suite with a microarchitectural design space that consists of 9 key parameters. Our results show that the models, built using a relatively small number of simulations, achieve high prediction accuracy (only 2.8% error in CPI estimates on average) across a large processor design space. Our models can potentially replace detailed simulation for common tasks such as the analysis of key microarchitectural trends or searches for optimal processor design points.

Method for coupling a power lead to a bond pad in an electronic module

Abstract: An electronic module and a method for coupling a power lead (32) to a bond pad (28) on a semiconductor die (17) within the electronic module. A clip support (13) having a slot (27) is coupled to a baseplate (11) via an isolation structure (14). The semiconductor die (17) is coupled to the baseplate (11) via an isolation structure (19). The power lead (32) is coupled to the isolation structure (14). The clip support (13) is coupled to the semiconductor die (17) via a clip (29), wherein a first end of the clip (29) is inserted in the slot (27) and a second end of the clip (29) is compressively mated with the semiconductor die (17). Compressively mating the clip (29) with the semiconductor die (17) eliminates the need for bond feet, thereby increasing the reliability of the module.

Low resistance probe for semiconductor

Abstract: A probe (10) that can be used for forming a low resistance electrical connection to a semiconductor die includes a contact (18) that is created on a compliant layer (12) which is supported by a substrate (11) Pressure applied to the contact (18) compresses the compliant layer (11) which causes a distal end of the contact (18) to move in a motion that is substantially equal to an arc As the contact (18) moves through the arc motion, it scrubs across a bonding pad of a semiconductor die and breaks through oxide that typically forms on the bonding pad thereby forming a low resistance electrical connection to the bonding pad

Physical insights regarding design and performance of independent-gate FinFETs

Abstract: Important physical insights regarding the design and performance of independent-gate FinFETs, e.g., the MIGFET , are gained from measured data and predictions from our process/physics-based double-gate (DG) MOSFET model (UFDG) in Spice3. Inversion charge-centroid shifting, modulated by gate biases as well as by quantum-confinement and short-channel effects, underlies the sensitivity of the MIGFET (front-gate) threshold voltage to the back-gate bias. MIGFET design and operation-mode options are examined for optimizing circuit applications. Further, novel design of a single-device RF mixer and a double-balanced counterpart using MIGFETs is studied with UFDG/Spice3. Reasonably good MIGFET mixers, with regard to conversion gain and linearity with small-size/low-voltage/low-power requirements, can be achieved with optimal biases on the two gates and good design of the MIGFET structure.

Semiconductor memory device and method of formation

Abstract: A semiconductor memory device is formed having a substrate (12). A diffusion (14) is formed within the substrate (12). A first vertical transistor stack (122) is formed. A second vertical transistor stack (124) is formed. The first vertical transistor stack (122) has a transistor (100) underlying a transistor (104). The second vertical transistor stack (124) has a transistor (102) underlying a transistor (106). The transistors (100 and 104) are connected in series, and the transistors (102 and 106) are connected in series. In a preferred form, transistors (100 and 102) are electrically connected as latch transistors for a semiconductor memory device and transistors (106 and 104) are connected as pass transistors. Two vertical stacks (126 and 128) form electrical interconnections (118 and 120) and resistive devices (134 and 138) for the semiconductor memory device.