Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Method of using sub-rate slots in an ultrawide bandwidth system

Abstract: A method is provided to pass information in a wireless network. The available channel time in the network is first divided into a plurality of sequential superframes. Some devices may need to transmit during every superframe, but others will only need to transmit during a fraction of the superframes. These devices are assigned sub-rate time slots in the superframes at sub-rates that must be a power of two. In other words, they can only be assigned sub-rate time slots every second superframe, every fourth superframe, every eighth superframe, etc. This allows the sub-rate time slots to be spread more evenly throughout the plurality of sequential superframes, and minimizes the amount of overlap possible.

Polaris: A System-Level Roadmap for On-Chip Interconnection Networks

Abstract: Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the increasing on-chip communication demand among the computation elements necessitates the use of scalable, nigh-bandwidth network-on-chip (NoC) fabrics. As transistor feature sizes are further miniaturized leading to rapidly increasing amounts of on-chip resources, more complicated and powerful NoC architectures become feasible that can support more sophisticated and demanding applications. Given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design space to identify the architecture(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris 1, a system-level roadmap for on-chip interconnection networks that guides designers towards the most suitable network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that will run over this network(s). Polaris explores the plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While the Polaris roadmapping toolchain is extensible so new traffic, network designs, and processes can be added, the current version of the roadmap already incorporates 7,872 NoC design points. Polaris is rapid and iterates over all these NoC architectures within a tractable run time of 125 hours on a typical desktop machine, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results.

DC offset correction for direct conversion receivers

Abstract: A direct current (DC) offset correction system for a direct conversion receiver and corresponding receiver and methods facilitate reduction of DC offsets in such receivers. One method includes calibrating a DC offset correction system in a closed loop configuration over each of a plurality of gain settings to provide a plurality of offset data for an operating mode of the direct conversion receiver; selecting one of the plurality of offset data based on a current gain setting of the direct conversion receiver as supplied, e.g., by an AGC system; and operating the DC offset correction system in an open loop configuration using the one of the plurality of offset data to correct for a DC offset in the direct conversion receiver.

Semiconductor memory cell having a trench structure

Abstract: In one embodiment, a semiconductor memory cell (10) having a trench (24) and access transistor (54) formed in a well region (20). The trench (24) substantially contains an inverter (60) which is electrically coupled to ground and power signals by buried layers (12, 18) in the substrate (11). The inverter (60) has a toroidal, shared-gate electrode (40) which electrically controls a driver transistor (32) in the wall (26) of the trench (24), and a thin-film load transistor (42) in the central portion of the trench (24). A portion of the toroidal, shared gate electrode extends to an adjacent well region (20') and contacts well region (20') at cell node (13'). A ground signal is provided to load transistor (42) at the bottom surface (28) of the trench (42). A supply signal is provided by a buried layer (18) which is integral with driver transistor (32).

Three Dimensional Integrated Passive Device And Method Of Fabrication

Abstract: An integrated passive device ( 20 ) includes a first wafer ( 22 ), a first integrated device ( 28 ) formed on a first surface ( 24 ) of the wafer ( 22 ), and a second integrated device ( 30 ) formed on a second surface ( 26 ) of the wafer ( 22 ), the second surface ( 26 ) opposing the first surface ( 24 ). A microelectromechanical (MEMS) device ( 72 ) includes a second wafer ( 74 ) having a MEMS component ( 76 ) formed thereon. The integrated passive device ( 20 ) and the MEMS device ( 72 ) are coupled to form an IPD/MEMS stacked device ( 70 ) in accordance with a fabrication process ( 90 ). The fabrication process ( 90 ) calls for forming ( 94 ) the second integrated device ( 30 ) on the second surface ( 26 ) of the wafer ( 22 ), constructing ( 100 ) the MEMS component ( 76 ) on the wafer ( 74 ), coupling ( 104 ) the wafers ( 22, 74 ), then creating the first integrated device ( 28 ) on the first surface ( 24 ) of the first wafer ( 22 ).