Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

High performance overmolded electronic package

Abstract: A package for containing high performance electronic components, such as high speed integrated circuits (ICs). The package bears a substrate of multiple layers having a cavity therein. Leads may be placed within holes in the substrate and soldered or otherwise electrically connected to conductive patterns or layers in the substrate. A thermally conductive insert is attached to one side of the substate. The insert has a pedestal which protrudes through the cavity in the substrate. An electronic component, such as an IC may then be mounted on the pedestal and electrically connected to a conductive metal pattern on one of the layers of the substrate. This assembly may then be coated with a dielectric material to form the package body, leaving the distal ends of the leads and the back side of the insert exposed. Since the IC chip or other component is directly mounted on the insert, waste heat generated by the chip may be directly channeled outside the package through the insert which effectively forms one wall of the package. The exposed leads may be formed into the desired configuration, including shapes suitable for surface mount technology. The use of a multiple layer substate permits the inclusion of ground and power planes for high performance circuits, such as emitter coupled logic (ECL) gate arrays, within the package itself.

Impact of Deposition and Annealing Temperature on Material and Electrical Characteristics of ALD HfO2

Abstract: Hafnium oxide is one of the most promising high-k materials to replace as a gate dielectric. Here we report material and electrical characterization of atomic layer deposition (ALD) hafnium oxide and the correlations between the results. The films were deposited at 200, 300, or 370°C and annealed in a nitrogen ambient at 550, 800, and 900°C. Results indicate that deposition temperature controls both the material and the electrical properties. Materials and electrical properties of films deposited at 200°C are most affected by annealing conditions compared to films deposited at higher temperatures. These films are amorphous as deposited and become polycrystalline after 800°C anneals. Voids are observed after a 900°C anneal for the 200°C deposited films. The 200°C deposited films have charge trapping and high leakage current following anneals at 900°C. The 300°C deposited films have lower chlorine content and remain void-free following high-temperature anneals. These films show a thickness-dependent crystal structure. Annealing the films reduces leakage current by four orders of magnitude. Finally, films deposited at 370°C have the highest density, contain the least amount of impurities, and contain more of the monoclinic phase of than those deposited at 300 and 200°C. The best electrical performance was obtained for films deposited at 370°C. © 2004 The Electrochemical Society. All rights reserved.

Power Efficiency and Linearity Enhancement Using Optimized Asymmetrical Doherty Power Amplifiers

Abstract: This paper investigates the virtues of the asymmetrical Doherty power amplifier (PA) for improving the average power efficiency, linearity, and peak envelope power. It commences with an in-depth study of the effects of increasing the size of the peaking amplifier's transistor and its conduction angle on the Doherty PA's RF performance. In particular, the impact of the extended current profile of the peaking amplifier and reduced turn-on effects on the soft-turn characteristic are thoroughly analyzed, and their impacts on the average efficiency and peak power are deduced. Furthermore, the aggravation of the memory effects that accompany the gm3-based nonlinear distortion cancellation is experimentally demonstrated. Two asymmetrical Doherty PAs prototypes are fabricated using 80 W and 150 W laterally diffused metal oxide semiconductor field-effect transistors to individually improve average efficiency and linearity. When driven with a four carrier wideband code division multiple access (4C-WCDMA) signal, the asymmetrical Doherty PA allowed for excellent drain efficiency of approximately 50%, along with high linearity of approximately -50 dBc , using a memory polynomial digital predistorter at an average output power of 50 W. To the best of the authors' knowledge, this achieved efficiency is the highest reported in the literature for a high-power Doherty PA implemented in LDMOS technology.

Method for making a semiconductor device with strain enhancement

Abstract: A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.

Stacked die semiconductor device

Abstract: A stacked multichip package (100) has a base carrier (102) having a top side (108) and a bottom side (110), a bottom integrated circuit die (104) having a bottom surface (112) attached to the base carrier top side (108), and an opposing, top surface (114). The top surface (114) has a peripheral area including a plurality of first bonding pads and a central area (120). A bead (124) is formed on the top surface (114) of the bottom die (104) between the peripheral area and the central area (120). A top integrated circuit die (106) having a bottom surface is positioned over the bottom die (104) and the bottom surface of the top die (106) is attached to the top surface (114) of the bottom die (104) via the bead (124). The bead (124) maintains a predetermined spacing between the bottom die (104) and the top die (106) so that wirebonds of first wires (122) connecting the bottom die (104) to the base carrier (102) are not damaged when the top die (106) is attached to the bottom die (104).