Institution
Freescale Semiconductor
About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..
Topics: Layer (electronics), Signal, Transistor, Integrated circuit, Amplifier
Papers published on a yearly basis
Papers
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TL;DR: In this paper, a bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure (11) having a stiff structural component (501, 502) positioned above and affixed to a conductive metal pad (103) formed in a last metal layer.
Abstract: A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure (11) having a stiff structural component (501, 502) positioned above and affixed to a conductive metal pad (103) formed in a last metal layer (104). The die test structure (11) may also include a dedicated support structure (41) below the conductive metal pad which includes a predetermined pattern of metal lines formed in the interconnect layers (18, 22, 26). After mounting the integrated circuit in a test device, a shear knife (601) is positioned for lateral movement to cause the shear knife to contact the stiff structural component (501). Any damage to the die test structure caused by the lateral movement of the shear knife may be assessed to evaluate the mechanical integrity of the interconnect stack.
41 citations
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01 Jul 2003TL;DR: In this paper, an integrated circuit with a plurality of bond pads comprising a bond-pad metal was shown to be plated using an activation plate, and the activation plate also included the bondpad metal.
Abstract: The invention provides a method of plating an integrated circuit. An activation plate is positioned adjacent to at least one integrated circuit. The integrated circuit includes a plurality of bond pads comprising a bond-pad metal, and the activation plate also comprises the bond-pad metal. A layer of electroless nickel is plated on the bond pads and the activation plate, and a layer of gold is plated over the layer of electroless nickel on the bond pads and the activation plate. An integrated circuit with bond pads plated using the activation plate, and a system for plating an integrated circuit is also disclosed.
41 citations
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02 Mar 1992TL;DR: In this paper, a vertical transistor has a substrate (12), a control electrode conductive layer (18), which functions as a control or gate electrode, and a sidewall dielectric layer (22) is formed laterally adjacent the control electrode and overlying the substrate.
Abstract: A vertical transistor (10) has a substrate (12) and a control electrode conductive layer (18), which functions as a control or gate electrode. A sidewall dielectric layer (22) is formed laterally adjacent the control electrode conductive layer (18) and overlying the substrate (12). The conductive layer (18) at least partially surrounds a channel region (30). A vertical conductive region is formed within a device opening wherein a bottom portion of the conductive region is a first current electrode (28). A middle portion of the vertical conductive region is the channel region (30). A top portion of the vertical conductive region is a second current electrode (34).
41 citations
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14 Nov 1996TL;DR: In this paper, a look ahead feature for the valid bit array is provided, such that during a read of the cache, the valid bits for a next instruction is checked with the same index used to read the current instruction, so that the program can remain active as long as the program is in a loop which can be contained entirely within the cache.
Abstract: A data processing system (20) has a cache (26) that does not use a TAG array for storing a TAG address as in a conventional cache. The cache (26), according to one embodiment, uses a state machine (30) for transitioning the cache (26) to an active state in response to a change of flow instruction which is a short backward branch instruction of a predetermined displacement. The predetermined displacement is less than the number of entries in the cache (26), so the cache can remain active as long as the program is in a loop which can be contained entirely within the cache. A look ahead feature for the valid bit array is provided that associates the valid bit for a current instruction with a previous instruction, such that during a read of the cache, the valid bit for a next instruction is checked with the same index used to read the current instruction.
41 citations
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30 Sep 2013TL;DR: In this paper, a gate structure is formed over the logic portion comprising a high k dielectric and a metal gate, which is then removed from the logic part leaving a portion of the second layer over the control gate and the select gate.
Abstract: A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate.
41 citations
Authors
Showing all 7673 results
Name | H-index | Papers | Citations |
---|---|---|---|
David Blaauw | 87 | 750 | 29855 |
Krishnendu Chakrabarty | 79 | 996 | 27583 |
Rajesh Gupta | 78 | 936 | 24158 |
Philippe Renaud | 77 | 773 | 26868 |
Min Zhao | 71 | 547 | 24549 |
Gary L. Miller | 63 | 306 | 13010 |
Paul S. Ho | 60 | 475 | 13444 |
Ravi Subrahmanyan | 59 | 353 | 14244 |
Jing Shi | 53 | 222 | 10098 |
A. Alec Talin | 52 | 311 | 12981 |
Chi Hou Chan | 48 | 511 | 9504 |
Lin Shao | 48 | 380 | 12737 |
Johan Åkerman | 48 | 306 | 9814 |
Philip J. Tobin | 47 | 186 | 6502 |
Alexander A. Demkov | 47 | 331 | 7926 |