Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

I/q mismatch compensation in an ofdm receiver in presence of frequency offset

Abstract: A receiver for an orthogonal frequency division multiplex radio signal in which a carrier frequency is modulated by sub-carrier signals (S1) coded with data Analogue signal processing means (3 to 12) produces base-band analogue signals (I-Rx, Q-Rx) in phase quadrature and analogue-to-digital converters (13, 14) convert the analogue signals to phase quadrature digital signals (x1(n), xq(n)) The digital signal processor includes the OFDM demodulator (15) and mismatch compensation (17, 18) The mismatch compensation (17, 18) combines each of the reproduced sub-carrier signals (R1) with a limited number of the reproduced sub-carrier signals (R1-Rk) according to respective frequency offset coefficient (1, k) that is a function of an estimated value of the offset ( fc) of the reference frequency relative to the carrier frequency

Modified hybrid orientation technology

Abstract: A semiconductor process and apparatus includes forming first and second metal gate electrodes (151, 161) over a hybrid substrate (17) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). By forming the first gate electrode (151) over a first SOI substrate (90) formed by depositing (100) silicon and forming the second gate electrode (161) over an epitaxially grown (110) SiGe substrate (70), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (161) having improved hole mobility.

Differential capacitive sensor and method of making same

Abstract: A differential capacitive sensor (50) includes a movable element (56) pivotable about a rotational axis (60). The movable element (56) includes first and second sections (94, 96). The first section (94) has an extended portion (98) distal from the rotational axis (60). A static layer (52) is spaced away from a first surface (104) of the moveable element (56), and includes a first actuation electrode (74), a first sensing electrode (64), and a third sensing electrode (66). A static layer (62) is spaced away from a second surface (106) of the moveable element (56) and includes a second actuation electrode (74), a second sensing electrode (70), and a fourth sensing electrode (72). The first and second electrodes (64, 70) oppose the first section (94), the third and fourth electrodes (66, 72) oppose the second section (96), and the first and second electrodes (68, 74) oppose the extended portion (98).

The Head of the Class

Abstract: Any time a person uses a wireless communications device, the equipment will always have some sort of power amplifier (PA) on board to boost the low-level analog signal to a level suitable to maintain adequate signal-to-noise ratio (SNR) over the communication link. There are a variety of applications (and many more to come in the future) requiring PAs of various power levels.

Method of forming a semiconductor device having conductive bumps without using gold

Abstract: A semiconductor device (10) includes a solder bump (40) that is formed using a gold-free under-bump metallurgy (UBM) (21). In a preferred embodiment, UBM (21) includes a diffusion barrier layer (22) of chromium and a metallic layer (24) of copper. The bump layer metallurgy (31) is deposited directly on the metallic layer, without an intervening gold layer. To overcome problems associated with a native oxide layer (26) which forms on the metallic layer, especially on copper, the bump metallurgy includes a seed layer (32) of tin that is deposited prior to a bulk lead layer (34). The bump metallurgy includes a final metallic layer (36) having sufficient tin to make a bump having approximately 97% Pb and 3% tin.