Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Apparatus and method for time ordering events in a system having multiple time domains

Abstract: A system and method time orders events that occur in various portions of the system (10) where different time domains (12, 22, 32) exist. Timestamping circuitry (40) is provided in each of a plurality of functional circuits or modules (14, 24, 34). The timestamping circuitry provides a message that indicates a point in time when a predetermined event occurs. An interface module (70) is coupled to each of the plurality of functional circuits (14, 24, 34). The interface module provides control information to the plurality of functional circuits to indicate at least one operating condition that triggers the predetermined event, and to optionally specify a message format. The interface module provides a timestamping message from one, several or all time domains at a common interface port (90).

Integrated circuit memory device and structural layout thereof

Abstract: A memory cell layout achieves a reduced cell area. In one embodiment, a six transitor (6T) SRAM cell has two vertical thin-film transistors (18 and 20) as load transistors, two transfer transistors (10 and 12), two latch transistors (14 and 16), and two storage nodes. NODE 1 and NODE 2 of the cell each have a minimum feature defined by trenches (60). Four of five interconnects associated with each node are located within the respective trench. For example in NODE 1, a drain of latch transistor (14), a gate of latch transistor (16), a drain of load transistor (18), and a current electrode of transfer transistor (10) are electrically coupled within or beneath one trench (60). A remaining interconnection of NODE 1, a gate of load transistor 20, is located within the trench associated with NODE 2. Thus, ten interconnects of the memory cell are contained within areas defined by two minimum features.

Microarchitecture Sensitive Empirical Models for Compiler Optimizations

Abstract: This paper proposes the use of empirical modeling techniques for building microarchitecture sensitive models for compiler optimizations. The models we build relate program performance to settings of compiler optimization flags, associated heuristics and key microarchitectural parameters. Unlike traditional analytical modeling methods, this relationship is learned entirely from data obtained by measuring performance at a small number of carefully selected compiler/microarchitecture configurations. We evaluate three different learning techniques in this context viz. linear regression, adaptive regression splines and radial basis function networks. We use the generated models to a) predict program performance at arbitrary compiler/microarchitecture configurations, b) quantify the significance of complex interactions between optimizations and the microarchitecture, and c) efficiently search for 'optimal' settings of optimization flags and heuristics for any given microarchitectural configuration. Our evaluation using benchmarks from the SPEC CPU2000 suits suggests that accurate models (\le 5% average error in prediction) can be generated using a reasonable number of simulations. We also find that using compiler settings prescribed by a model-based search can improve program performance by as much as 19% (with an average of 9.5%) over highly optimized binaries.

CMOS integration with metal gate and doped high-K oxides

Abstract: A method and apparatus are described for fabricating single metal gate electrodes ( 35, 36 ) over a high-k gate dielectric layer ( 31, 32 ) that is separately doped in the PMOS and NMOS device areas ( 96, 97 ) by forming first capping oxide layer ( 23 ) with a first dopant species on a high-k gate dielectric layer ( 22 ) in at least the NMOS device area and also forming second capping oxide layer ( 27 ) with a second dopant species on a high-k gate dielectric layer ( 22 ) in at least the PMOS device area, where the first and second dopant species are diffused into the gate dielectric layer ( 22 ) to form a first fixed charge layer ( 31 ) in the PMOS device area of the high-k gate dielectric area and a second fixed charge layer ( 32 ) in the NMOS device area of the high-k gate dielectric area.

Contact structure and method

Abstract: A semiconductor device structure including a contact and a method for its fabrication are disclosed. In accordance with one embodiment of the disclosure, a contact is formed between a monocrystalline silicon substrate and an overlying silicon layer. A silicon substrate is provided which has a first insulating layer formed thereon. A layer of silicon is deposited and patterned over the insulator layer. The patterned silicon layer is then oxidized and a contact opening is etched through the first insulator layer and the silicon dioxide is expose portions of the silicon substrate and an adjacent portion of the patterned silicon layer. A further layer of polycrystalline silicon is then selectively deposited onto the exposed portions of the substrate and silicon layer to form an electrical connection between the two.