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Institution

Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..


Papers
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Patent
02 Mar 1999
TL;DR: In this paper, a fuse detect circuit (124) is proposed to limit the voltage drop across the fuse to an absolute value independent of a power supply voltage applied to the integrated circuit memory.
Abstract: Fuses and detect circuits (124) in an integrated circuit memory (100) include a copper fuse (208) and a fuse state detect stage (202) for detecting the open circuit state or the closed circuit state of the fuse (208). The fuse detect circuit (124) provides an output signal corresponding to the state of the fuse and during detecting, limits a voltage drop across the fuse to an absolute value independent of a power supply voltage applied to the integrated circuit memory. The fuse detect circuit (124) operates at power up of the integrated circuit memory (100) and is disabled after the state of the fuse is detected and latched, and the power supply is sufficient for reliable operation of the integrated circuit memory (100). By limiting the voltage drop across a blown copper fuse (208), a potential electro-migration problem is reduced.

40 citations

Journal ArticleDOI
TL;DR: The nonmonotonic behavior of power/ground noise with respect to the transition time tr is investigated for an inductive power distribution network with a decoupling capacitor and an equivalent transition time that corresponds to resonance is presented to accurately estimate the worst case power/ ground noise in the time domain.
Abstract: The nonmonotonic behavior of power/ground noise with respect to the transition time tr is investigated for an inductive power distribution network with a decoupling capacitor. The worst case power/ground noise obtained with fast switching characteristics is shown to be significantly inaccurate. An equivalent transition time that corresponds to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. Furthermore, the sensitivity of the ground noise to the decoupling capacitance Cd and parasitic inductance Lg is evaluated as a function of the transition time. Increasing the decoupling capacitance is shown to efficiently reduce the noise for transition times smaller than twice the LC time constant, tr les 2radic(LgCd). Alternatively, reducing the parasitic inductance Lg is shown to be effective for transition times greater than twice the LC time constant, tr ges 2radic(LgCd). The peak noise occurs when the transition time is approximately equal to twice the LC time constant, tr ap 2radic(LgCd) , referred to as the equivalent transition time for resonance.

40 citations

Patent
27 Jul 2005
TL;DR: In this paper, a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting of a source (14) electrode and a drain (16) electrode adjacent to an intervening gate and channel (23) connected via source/drain extensions.
Abstract: A semiconductor device (10) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting (32) of a source (14) electrode and a drain (16) electrode adjacent to an intervening gate (18) and channel (23) connected via source/drain extensions (22, 24) which form a fin. At small dimensions, ion implanting may cause irreparable crystal damage to any thin areas of silicon such as the fin area. To permit a high concentration/low resistance source/drain extension, a sacrificial doping layer (28, 30) is formed on the sides of the fin area. Dopants from the sacrificial doping layer are diffused into the source electrode and the drain electrode using heat. Subsequently a substantial portion, or all, of the sacrificial doping layer is removed from the fin.

40 citations

Journal ArticleDOI
TL;DR: This paper presents two symbolic model checking algorithms for the verification of analog/mixed-signal circuits that utilizes binary decision diagrams while the second is a bounded model checker that uses a satisfiability modulo theory solver.
Abstract: This paper presents two symbolic model checking algorithms for the verification of analog/mixed-signal circuits. The first model checker utilizes binary decision diagrams while the second is a bounded model checker that uses a satisfiability modulo theory solver. Both methods have been implemented, and preliminary results are promising.

40 citations

Patent
08 Aug 2013
TL;DR: In this article, a process integration for fabricating nonvolatile memory (NVM) cells having recessed control gates on a first substrate area, which are encapsulated in one or more planar dielectric layers, prior to forming in-laid high-k metal select gates and CMOS transistor gates in first and second substrate areas.
Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells having recessed control gates ( 118, 128 ) on a first substrate area ( 111 ) which are encapsulated in one or more planar dielectric layers ( 130 ) prior to forming in-laid high-k metal select gates and CMOS transistor gates ( 136, 138 ) in first and second substrate areas ( 111, 113 ) using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

40 citations


Authors

Showing all 7673 results

NameH-indexPapersCitations
David Blaauw8775029855
Krishnendu Chakrabarty7999627583
Rajesh Gupta7893624158
Philippe Renaud7777326868
Min Zhao7154724549
Gary L. Miller6330613010
Paul S. Ho6047513444
Ravi Subrahmanyan5935314244
Jing Shi5322210098
A. Alec Talin5231112981
Chi Hou Chan485119504
Lin Shao4838012737
Johan Åkerman483069814
Philip J. Tobin471866502
Alexander A. Demkov473317926
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20211
20203
201910
201826
201779
2016267