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Institution

Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..


Papers
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Patent
24 Jul 2003
TL;DR: In this paper, the authors proposed a nonvolatile memory (NVM) cell, which uses a storage dielectric as the storage element, has a top dielectrically between a gate and the storage, and a bottom-dielectric between a semiconductor substrate and the NVM.
Abstract: A non-volatile memory (NVM) cell, which uses a storage dielectric as the storage element, has a top dielectric between a gate and the storage dielectric and a bottom dielectric between a semiconductor substrate and the storage dielectric. The top dielectric includes a relatively thick and high k dielectric layer and an interfacial layer. The interfacial layer is very thin and has a higher k than silicon oxide. The bottom dielectric layer is preferably silicon oxide because of its interfacial and tunneling properties. The cell thus has benefits resulting from a well-passivated, high k top dielectric in combination with a bottom dielectric of silicon oxide.

39 citations

Patent
11 Apr 2007
TL;DR: In this article, a technique for tracing processes executing in a multi-threaded processor includes forming a trace message that includes a virtual core identification (VCID) that identifies an associated thread.
Abstract: A technique for tracing processes executing in a multi-threaded processor includes forming a trace message that includes a virtual core identification (VCID) that identifies an associated thread. The trace message, including the VCID, is then transmitted to a debug tool.

39 citations

Patent
22 Jan 2010
TL;DR: In this paper, a method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and a second refresh on a second portion of DRAM with a higher refresh rate.
Abstract: A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate.

39 citations

Journal ArticleDOI
TL;DR: An on-chip noise sensor dedicated to the study of circuit susceptibility to electromagnetic interferences and a demonstration of the sensor measurement performances and benefits is proposed.
Abstract: With the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of noncompliance becomes critical for circuit designers. However, an on-chip characterization of noise is still necessary for model validation and design optimization. Although different on-chip measurement solutions have been proposed for emission issue characterization, no on-chip measurement methods have been proposed to address the susceptibility issues. This paper presents an on-chip noise sensor dedicated to the study of circuit susceptibility to electromagnetic interferences. A demonstration of the sensor measurement performances and benefits is proposed through a study of the susceptibility of a digital core to conducted interferences. Sensor measurements ensure a better characterization of actual coupling of interferences within the circuit and a diagnosis of failure origins.

39 citations

Patent
12 Jan 1995
TL;DR: In this paper, a miniature virtual image color display with a viewing aperture was proposed, the display including a plurality of semiconductor chips, each defining a set of pixels, and the plurality of pixels of each semiconductor chip formed a complete real image.
Abstract: A miniature virtual image color display having a viewing aperture, the display including a plurality of semiconductor chips each defining a plurality of pixels. The plurality of pixels of each semiconductor chip form a complete real image and each semiconductor chip is formed to provide the complete real image in a different color. An optical system combines the different colored real images and produces, from the plurality of complete real images, a single virtual image in color. The single virtual image is magnified so as to be viewable through the viewing aperture. The miniature virtual image display is designed to be incorporated into a communications receiver, such as a pager or two-way radio.

39 citations


Authors

Showing all 7673 results

NameH-indexPapersCitations
David Blaauw8775029855
Krishnendu Chakrabarty7999627583
Rajesh Gupta7893624158
Philippe Renaud7777326868
Min Zhao7154724549
Gary L. Miller6330613010
Paul S. Ho6047513444
Ravi Subrahmanyan5935314244
Jing Shi5322210098
A. Alec Talin5231112981
Chi Hou Chan485119504
Lin Shao4838012737
Johan Åkerman483069814
Philip J. Tobin471866502
Alexander A. Demkov473317926
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20211
20203
201910
201826
201779
2016267