Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Self-aligned magnetic clad write line and its method of formation

Abstract: A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240 a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (264), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.

Single proof mass, 3 axis mems transducer

Abstract: A transducer is provided herein which comprises an unbalanced proof mass (51), and which is adapted to sense acceleration in at least two mutually orthogonal directions. The proof mass (51) has first (65) and second (67) opposing sides that are of unequal mass.

Wait mode power reduction system and method for data processor

Abstract: A method and apparatus for reducing power consumption in a data processing system by interrupting the supply of clocking pulses to selected portions of the system in response to a power-down signal provided by a data processing portion of the system only if the state of a respective control signal indicates that that particular portion of the system is then disabled or otherwise inhibited from interrupting the operation of the data processing portion.

A Monolithic CMOS-MEMS 3-Axis Accelerometer With a Low-Noise, Low-Power Dual-Chopper Amplifier

Abstract: This paper reports a monolithically integrated CMOS-MEMS three-axis capacitive accelerometer with a single proof mass. An improved DRIE post-CMOS MEMS process has been developed, which provides robust single-crystal silicon (SCS) structures in all three axes and greatly reduces undercut of comb fingers. The sensing electrodes are also composed of the thick SCS layer, resulting in high resolution and large sensing capacitance. Due to the high wiring flexibility provided by the fabrication process, fully differential capacitive sensing and common-centroid configurations are realized in all three axes. A low-noise, low- power dual-chopper amplifier is designed for each axis, which consumes only 1 mW power. With 44.5 dB on-chip amplification, the measured sensitivities of x-, y-, and z-axis accelerometers are 520 mV/g, 460 mV/g, and 320 mV/g, respectively, which can be tuned by simply changing the amplitude of the modulation signal. Accordingly, the overall noise floors of the x-, y-, and z-axis are 12 mug/radicHz , 14 mug/radicHz, and 110 mug/radicHz, respectively, when tested at around 200 Hz.