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Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..


Papers
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Patent
23 Jan 2006
TL;DR: In this article, a selected memory cell is coupled to the local data line pair (116, 118 ) to develop a differential LDC, which is subsequently amplified to form an amplified differential local LDC.
Abstract: In a memory ( 100 ), a local data line pair ( 116, 118 ) is precharged to a first logic state and a global data line pair ( 101, 104 ) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair ( 116, 118 ) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair ( 101, 104 ) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.

127 citations

Journal ArticleDOI
TL;DR: In this paper, a cascade of buck and boost converter is presented, which transitions between the modes seamlessly to provide a tracking power conversion function for modulating the power supply of a variable envelope radio frequency (RF) power amplifier.
Abstract: A cascade of buck and boost converter is presented here. The control operates in a manner that the converter is either in buck or boost (BOB) mode on a cycle by cycle basis. It transitions between the modes seamlessly to provide a tracking power conversion function for modulating the power supply of a variable envelope radio frequency (RF) power amplifier. The control algorithm and its implementation using switched capacitor circuits is described. Simulation and measured experimental results including converter efficiency, tracking accuracy, and spectrum at the output of the RF power amplifier are provided. This control technique allows seamless transition between the buck and boost modes while tracking RF envelopes with bandwidth greater than 100 kHz, and maintaining extreme accuracy and extremely low ripple. The efficiency of this converter operating at 1.68 MHz is close to 90% over a wide range of conversion ratios. The area of the power converter is extremely small allowing this to be integrated into a cellular telephone. The controller was integrated as part of a larger power management IC as well as a discrete IC.

126 citations

Journal ArticleDOI
TL;DR: The relationship between device feature size and device performance figures of merit (FoMs) is more complex for radio frequency (RF) applications than for digital applications as mentioned in this paper. But the authors in this paper focus on Si complementary metaloxide-semiconductor (CMOS), Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits.
Abstract: The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.

126 citations

Patent
17 Mar 1997
TL;DR: In this paper, a rapid thermal processing susceptor including a base having a planar surface and an upright sidewall extending around a periphery thereof and encircling a working portion of the planar surfaces is described.
Abstract: A rapid thermal processing susceptor including a base having a planar surface and an upright sidewall extending around a periphery thereof and encircling a working portion of the planar surface. The working portion and the sidewall define a cavity. A plurality of minimum contact points extend from the working portion into the cavity and are positioned to receive thereon a semiconductor wafer. A cover is receivable by the sidewall for enclosing the cavity.

124 citations

Patent
13 Dec 1999
TL;DR: An improved and novel fabrication method for magnetoresistive random access memory (MRAM) is provided in this paper, where a dielectric layer (40, 41) is deposited on the circuit, and trenches (42, 43) are formed in the dielectrics layer.
Abstract: An improved and novel fabrication method for magnetoresistive random access memory (MRAM) is provided. An MRAM device has memory elements and circuitry for managing the memory elements. The circuitry includes transistor (12a), digit line (29), etc., which are integrated on a substrate (11). The circuitry is fabricated first under the CMOS process and then magnetic memory elements (53, 54). A dielectric layer (40, 41) is deposited on the circuit, and trenches (42, 43) are formed in the dielectric layer. A blanket layer (46), which includes magnetic layers (48, 49) and a non-magnetic layer (50) sandwiched by the magnetic layers, is deposited on dielectric layer (41) and in the trenches. Then, the blanket layer outside the trenches is removed and MRAM elements (53, 54) are formed in the trenches.

123 citations


Authors

Showing all 7673 results

NameH-indexPapersCitations
David Blaauw8775029855
Krishnendu Chakrabarty7999627583
Rajesh Gupta7893624158
Philippe Renaud7777326868
Min Zhao7154724549
Gary L. Miller6330613010
Paul S. Ho6047513444
Ravi Subrahmanyan5935314244
Jing Shi5322210098
A. Alec Talin5231112981
Chi Hou Chan485119504
Lin Shao4838012737
Johan Åkerman483069814
Philip J. Tobin471866502
Alexander A. Demkov473317926
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20211
20203
201910
201826
201779
2016267