Institution
Freescale Semiconductor
About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..
Topics: Layer (electronics), Signal, Transistor, Integrated circuit, Voltage
Papers published on a yearly basis
Papers
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16 Dec 1996TL;DR: In this article, a method of fabricating a plurality of spaced apart submicron memory cells is described, including the steps of depositing a magnetoresistive system on a substrate formation.
Abstract: A method of fabricating a plurality of spaced apart submicron memory cells is disclosed, including the steps of depositing a magnetoresistive system on a substrate formation, depositing and patterning a first layer of material to form sidewalls, and depositing a second, selectively etchable, layer of material on the first layer of material, etching the second layer of material to define spacers on the sidewalls of the first layer of material, etching the magnetoresistive system, using the spacers as a mask, to define a plurality of spaced apart submicron magnetic memory cells, and depositing electrical contacts on the plurality of spaced apart submicron magnetic memory cells.
37 citations
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20 Nov 2007TL;DR: In this paper, the first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop, and then executes a reservation-based instruction that can change the execution state of a first thread.
Abstract: A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a reservation for a predetermined memory address. The first thread then executes a reservation-based instruction that can change the execution state of the first thread. Reservation circuitry of the processing device that was executing the first thread monitors the reservation. In the event that the reservation cleared, such as by the second thread modifying data at the predetermined memory address, the first thread is reinstated to its prior execution state. By using a hardware reservation mechanism to monitor for clearing of a set reservation, repeated memory accesses to the memory address by the first thread can be minimized or avoided while in the polling loop and other threads can be allowed to execute at the processing device with reduced interference from the waiting thread.
37 citations
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17 Nov 2008TL;DR: A twisted winding scheme for inductors that increases the localization of the magnetic field, reducing parasitic magnetic coupling by as much as 3100X and the edge-to-edge spacing of inductors by 10X and is validated in a 0.18 mum CMOS process.
Abstract: Parasitic magnetic coupling is a major design challenge for integrated circuit designers. Fundamentally, it originates in conventional spiral inductors because the magnetic field is not localized, extending far beyond the perimeter. This paper introduces a twisted winding scheme for inductors that increases the localization of the magnetic field, reducing parasitic magnetic coupling by as much as 3100X and the edge-to-edge spacing of inductors by 10X. These results are validated in a 0.18 mum CMOS process.
37 citations
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17 May 2000TL;DR: In this paper, a method for fast training of equalizers in a DMT system is proposed by normalizing the incoming receive signal via steps (108-116), where the convergence rate of the training algorithm becomes relatively independent of channel line length so that long line lengths may converge to optimal equalizer coefficients in short time periods.
Abstract: A method for fast training of equalizers in a DMT system begins by normalizing the incoming receive signal ( y ) via steps (108-116). By normalizing the signal, the convergence rate of the training algorithm becomes relatively independent of channel line length so that long line lengths may converge to optimal equalizer coefficients in short time periods. The method also iteratively adjusts the filter coefficients w over time by using an adaptive gain vector µ that is updated on a component-by-component basis on each iteration via steps (114-146). By allowing each component of the vector µ to iteratively adapt independent of all other components in the vector µ based upon the binary sign bit of both real and imaginary components of frequency domain gradient vectors G , a convergence to optimal equalizer filter coefficients will occur in a short period of time.
37 citations
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27 Sep 2004TL;DR: In this article, a cellular mobile station (101) including a modem processor (127) and memory (129) is shown to have different levels of memory to provide different deterministic access times.
Abstract: A cellular mobile station (101) including a modem processor (127) and memory (129). The memory includes instructions for the modem processor to perform layer 1 processor operations, layer 2 processor operations, and layer 3 processor operations. The modem processor executes the instructions to perform processor operations for the cellular mobile station to communication data as per a cellular communications protocol. In one example, the mobile station includes different levels of memory to provide different deterministic access times.
37 citations
Authors
Showing all 7673 results
Name | H-index | Papers | Citations |
---|---|---|---|
David Blaauw | 87 | 750 | 29855 |
Krishnendu Chakrabarty | 79 | 996 | 27583 |
Rajesh Gupta | 78 | 936 | 24158 |
Philippe Renaud | 77 | 773 | 26868 |
Min Zhao | 71 | 547 | 24549 |
Gary L. Miller | 63 | 306 | 13010 |
Paul S. Ho | 60 | 475 | 13444 |
Ravi Subrahmanyan | 59 | 353 | 14244 |
Jing Shi | 53 | 222 | 10098 |
A. Alec Talin | 52 | 311 | 12981 |
Chi Hou Chan | 48 | 511 | 9504 |
Lin Shao | 48 | 380 | 12737 |
Johan Åkerman | 48 | 306 | 9814 |
Philip J. Tobin | 47 | 186 | 6502 |
Alexander A. Demkov | 47 | 331 | 7926 |