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Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..


Papers
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Patent
15 Mar 2006
TL;DR: In this paper, a memory device is formed on a semiconductor substrate and a select gate electrode and a control gate electrode are formed adjacent to one another, and one of either the select gate or the control gate electrodes is recessed with respect to the other.
Abstract: A memory device is formed on a semiconductor substrate. A select gate electrode and a control gate electrode are formed adjacent to one another. One of either the select gate electrode or the control gate electrodes is recessed with respect to the other. The recess allows for a manufacturable process with which to form silicided surfaces on both the select gate electrode and the control gate electrode.

37 citations

Journal ArticleDOI
TL;DR: In this article, the effect of sputter pressure and additional anneals on electrical properties of indium tin oxide (ITO) thin layers was investigated and the results revealed that the lowest resistivity of 1.69×−10−4−4 ǫ cm was achieved at low pressure (1.2 ) and the highest transmittance of ~90% was obtained after a second anneal.

37 citations

Journal ArticleDOI
TL;DR: In this paper, a joint experimental and theoretical study of ultrathin hafnia films grown on Si (001) by atomic layer deposition for applications as a gate dielectric of a field effect transistor is presented.
Abstract: We present a joint experimental and theoretical study of ultrathin hafnia films grown on Si (001) by atomic layer deposition for applications as a gate dielectric of a field-effect transistor. The structural analysis by means of high-resolution transmission electron microscopy, electron diffraction, and x-ray diffractometry indicates films with thickness of 4 nm or less to be polycrystalline, predominantly monoclinic and textured, with the texture axis being the normal to the $(21\overline{1})$, $(11\overline{2})$, and their equivalent planes. Films with thickness around 10 nm consist of a mixture of monoclinic and tetragonal phases more or less randomly oriented. Films thicker than 25 nm are purely monoclinic with $(\overline{1}11)$ and (111) textures. Using density-functional theory we investigate surface energies of monoclinic and tetragonal hafnia films in search for thermodynamic means of controlling the film microstructure. We report the atomic and electronic structures of these films including the surface energy, work function, and electron affinity.

37 citations

Patent
30 Jun 2008
TL;DR: In this paper, a technique for joint detection of channel-coded signals in a multiple-input multiple-output (MIMO) system is proposed, which includes detecting, when a decoded signal associated with a first symbol stream passes a cyclic redundancy check, channel coded signals in the first and second symbol streams are detected using neighbor search algorithm (NSA) based detection.
Abstract: A technique for joint detection of channel-coded signals in a multiple-input multiple-output system includes detecting, when a decoded signal associated with a first symbol stream passes a cyclic redundancy check, channel-coded signals in the first symbol stream and a second symbol stream using minimum mean squared error with ordered successive interference cancellation (MMSE-OSIC) based detection. When the decoded signal associated with the first symbol stream fails the cyclic redundancy check, the channel-coded signals in the first and second symbol streams are detected using neighbor search algorithm (NSA) based detection.

37 citations

Patent
19 Dec 2006
TL;DR: In this paper, a memory cell is implemented using a semiconductor fin (105, 107) in which the channel region is along a sidewall of the fin between source and drains regions.
Abstract: A memory cell is implemented using a semiconductor fin (105, 107) in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate (731) adjacent to it and another other portion has the control gate (1001) adjacent to it with a charge storage structure there between. In some embodiments, independent control gate structures are located adjacent opposite sidewalls of the fin so as to implement two memory cells.

37 citations


Authors

Showing all 7673 results

NameH-indexPapersCitations
David Blaauw8775029855
Krishnendu Chakrabarty7999627583
Rajesh Gupta7893624158
Philippe Renaud7777326868
Min Zhao7154724549
Gary L. Miller6330613010
Paul S. Ho6047513444
Ravi Subrahmanyan5935314244
Jing Shi5322210098
A. Alec Talin5231112981
Chi Hou Chan485119504
Lin Shao4838012737
Johan Åkerman483069814
Philip J. Tobin471866502
Alexander A. Demkov473317926
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20211
20203
201910
201826
201779
2016267