Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

A 350 W, 790 to 960 MHz wideband LDMOS doherty amplifier using a modified combining scheme

Abstract: A modified Doherty combining scheme is proposed that eases the impedance matching requirement and enables excellent AM/AM, AM/PM, and wide bandwidth in practical designs A 350 W, 790 to 960 MHz symmetrical LDMOS Doherty amplifier measured 20 to 21 dB gain as well as peak and back-off efficiencies of 56% to 61% and 48% to 50% respectively across the band The amplifier achieved excellent linearization results when driven with wideband 20 and 50 MHz WCDMA signals and a 35 MHz GMSK signal

The Network Processing Forum switch fabric benchmark specifications: an overview

Abstract: The Network Processing Forum chartered a fabric benchmarking task group to establish a set of switch fabric benchmark specifications that allows the characterization of a wide range of switch fabrics for diverse networking applications. A unique characteristic of the benchmarks is their ability to produce comparable performance results for different switch fabrics, regardless of their underlying architecture and technology. This article provides an overview of the NPF fabric benchmark specifications by describing the various topics addressed by the standard as well as their potential impact.

Integration technique using thermal oxide select gate dielectric for select gate and apartial replacement gate for logic

Abstract: A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.

Method for making a semiconductor structure using silicon germanium

Abstract: A semiconductor substrate having a silicon layer (24,26,28) is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate (12,14,24,26,28) having an oxide layer (14) underlying the silicon layer (24,26,28). An amorphous or polycrystalline silicon germanium layer (32) is formed overlying the silicon layer (24,26,28). Alternatively, germanium is implanted into a top portion of the silicon layer (24,26,28) to form an amorphous silicon germanium layer (32). The silicon germanium layer (32) is then oxidized to convert the silicon germanium layer into a silicon dioxide layer (34) and to convert at least a portion of the silicon layer (24,26,28) into germanium-rich silicon (36,38). The silicon dioxide layer (34) is then removed prior to forming transistors (48,50,52) using the germanium-rich silicon (36,38). In one embodiment, the germanium-rich silicon (36,38) is selectively formed using a patterned masking layer (30) over the silicon layer (28) and under the silicon germanium layer (32). Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

Cladding of a conductive interconnect for programming a MRAM device using multiple magnetic layers

Abstract: A cladded conductive interconnect for programming a magnetoresistive memory device which includes a conductive material with a length, a first barrier conductive material positioned on the conductive material, and a multi-layer cladding region positioned along the length of the conductive material wherein the multi-layer cladding region includes N ferromagnetic layers, where N is a whole number greater than or equal to two, and wherein the multi-layer cladding region further includes at least one spacer layer, wherein the spacer layer can include a metal, an insulator, or an exchange interaction material, and wherein the spacer layer is sandwiched therebetween each adjacent ferromagnetic layer.