Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Compact harmonic filter design and fabrication using IPD technology

Abstract: An integrated passive device (IPD) on GaAs technology has been developed to meet the ever increasing needs of size and cost reduction in radio transmit module applications. Extensive electromagnetic (EM) simulations were used in the design of process technology and the optimization of inductor and harmonic filters design and layout. Parameters such as inductor shape, inner diameter, metal thickness, metal width and substrate thickness have been optimized to provide inductors with high quality factors. The technology includes the following features: 1) thick plated gold metal process to reduce resistive loss; 2) MIM capacitors using PECVD Si/sub 3/N/sub 4/ dielectric layer; 3) airbridges for inductor underpass and capacitor pick-up; and 4) 10mil finished GaAs substrate to improve inductor quality factor. Both lumped element circuit simulation and electromagnetic (EM) simulations have been used in the harmonic filter circuit design for fast design cycle time and high accuracy. This paper presents the EM simulation calibration and demonstrate the importance of using EM simulations in filter design in order to achieve success in first wafer fabrication. The fabricated IPD devices have insertion loss of 30dB with die size of 1.42mm/sup 2/ for high band (1710MHz -1910MHz) and 1.89mm/sup 2/ for low band (824MHz-915MHz) harmonic filters.

Solid-State Annealing Behavior of Two High-Pb Solders, 95Pb5Sn and 90Pb10Sn, on Cu Under Bump Metallurgy

Abstract: The solid-state annealing behavior of two high-lead solders, 95Pb5Sn and 90Pb10Sn (in wt.%), was examined. After reflow, Cu3Sn intermetallics formed on the Cu under bump metallurgy (UBM) for both solder alloys. However, solidstate annealing produced significantly different reaction morphologies for the two solder compositions. The Cu3Sn intermetallics spalled off faster at higher temperatures in the 95Pb5Sn solder. In the case of 90Pb10Sn solder, the Cu3Sn intermetallics continued to grow even after 1500 h at 170°C. The difference was explained by a two-step phenomenon—Sn diffusion from the bulk solder region to the solder/Cu3Sn interface (JSn), and subsequent intermetallic formation (ICu3Sn) by interdiffusion of Cu and Sn. For 95Pb5Sn, the relation, JSn ICu3Sn was suggested for the continuous intermetallic growth of the 90Pb10Sn solder. Although a small difference was expected between the two quantities in both solder alloys, the difference in the solid-state annealing behavior was dramatic.

Magnetoresistive random access memory device structures and methods for fabricating the same

Abstract: Magnetoelectric memory element structures and methods for making such structures using a barrier layer as a material removal stop layer are provided. The methods comprise forming a digit line (26) disposed at least partially within a dielectric layer (24). The dielectic material layer overlies an interconnect stack. A conductive barrier layer (40, 42) having a first portion (40) and a second portion (42) id deposited. The first portion overlies the digit line and the second portion is disposed within the void space and in electrical communication with the interconnect stack. A memory element layer (46) is formed overlying the first portion and an electrode layer (48) is deposited overlying the memory element layer. The electrode layer and the memory element layer are then patterned and etched.

Power on reset circuit

Abstract: A power on reset (POR) circuit for providing a reset pulse signal to a chip when power supply voltage, VDD, ramps up so that the chip always starts in a known state. The POR circuit generates the reset pulse as soon as VDD exceeds an assertion voltage. The assertion voltage is independent of the ramp rate of VDD. The POR circuit is shut off as soon as the reset signal is generated, thereby drawing zero steady state current from VDD. The re-arm time for the POR circuit is very small. The POR circuit does not reset the chip when there is a dynamic change in VDD.