Institution
Freescale Semiconductor
About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..
Topics: Layer (electronics), Signal, Transistor, Integrated circuit, Amplifier
Papers published on a yearly basis
Papers
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29 Jun 1998TL;DR: In this paper, an electronic component assembly is formed by mounting an EH component to the leads of a leadframe and encapsulating the leads and the EH with a package.
Abstract: An electronic component assembly (10) is formed by mounting an electronic component (15) to the leads (12) of a leadframe (18). The portions of the leadframe (18) that come in physical contact with the electronic component (15) are electrically connected to the electronic component with bonding wires (31) or by placing the bonding regions (30) of the electronic component (15) in direct physical contact with the tips (35) of the leads (12). A package (20) is used to encapsulate the leads (12) and the electronic component (15).
123 citations
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30 Jan 2001TL;DR: In this paper, a gate electrode is formed over the metal oxide layer, thereby exposing a portion of the metal oxide layer, which is then chemically reduced to a metal or a metal hydride.
Abstract: A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed portion of the metal oxide gate dielectric layer is then chemically reduced to a metal or a metal hydride. The metal or metal hydride is then removed with a conventional wet etch or wet/dry etch combination. The metal oxide layer may include a metal element such as zirconium, tantalum, hafnium, titanium, or lanthanum and may further include an additional element such as silicon or nitrogen. Reducing the metal oxide layer may includes annealing the metal oxide gate dielectric layer in an ambient with an oxygen partial pressure that is less than a critical limit for oxygen desorption at a given temperature. In another embodiment, reducing the metal oxide gate dielectric layer may include annealing the metal oxide layer while supplying a hydrogen-containing precursor such as silane, ammonia, germane, hydrogen, and hydrazine to the metal oxide gate dielectric layer. The gate electrode may comprise a gate electrode stack that includes a titanium nitride layer over the metal oxide gate dielectric layer and a silicon-containing capping layer over the titanium nitride layer.
123 citations
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26 Jan 1996TL;DR: In this paper, the authors show that the absence of physical contact between the conductive balls and the test contacts during testing reduces the likelihood that the balls will inadvertently fuse to the test socket or create solder build-up on the test contact.
Abstract: A ball grid array semiconductor device (30) includes a plurality of conductive balls (36) and a plurality of conductive castellations (18) around its periphery as redundant electrical connections to a semiconductor die (12). During testing of the device in a test socket (50), the conductive castellations are contacted by test contacts (54). The test contacts do not come in physical contact with the conductive balls. As a result, when testing is performed at elevated temperatures near the melting point of the conductive balls, the conductive balls are not deformed by the test contacts, thereby eliminating cosmetic-defects. Additionally, the absence of physical contact between the conductive balls and the test contacts during testing reduces the likelihood that conductive balls will inadvertently fuse to the test socket or create solder build-up on the test contacts.
122 citations
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01 Nov 1996TL;DR: In this paper, a method of interconnecting transistors and other devices in order to optimize area of a layout of a cell while honoring performance constraints and enhancing yield starts with a prerouting step.
Abstract: A method of interconnecting transistors and other devices in order to optimize area of a layout of a cell while honoring performance constraints (1502) and enhancing yield starts with a prerouting step (152) that routes adjacent transistors using diffusion wiring (1506), routes power and ground nets (1508), routes aligned gates (1510), routes all remaining aligned source/drain nets as well as any special nets (1512). Next, all of the remaining nets are routed using an area based router (1408). Nets are order based on time criticality or net topology (1602). A routing grid is assigned for all the layers to be used in routing (1604). An initial coarse routing is performed (1606). Wire groups are assigned to routing layers (1608). Routing is improved and vias are minimized (1610). A determination is then made whether the routing solution is acceptable (1612). If the routintg solution is not acceptable, the routing space is expanded and routing costs and via costs are modifyied to improve the routing solution. Finally, the best routing solution is picked (1414).
122 citations
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18 Apr 2003
TL;DR: In this paper, a circuit device (15 ) is placed within an opening of a conductive layer (10 ) which is then partially encapsulated with an encapsulant ( 24 ) so that the active surface of the circuit device is coplanar with the conductive surface (10 ).
Abstract: A circuit device ( 15 ) is placed within an opening of a conductive layer ( 10 ) which is then partially encapsulated with an encapsulant ( 24 ) so that the active surface of the circuit device ( 15 ) is coplanar with the conductive layer ( 10 ). At least a portion of the conductive layer ( 10 ) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device ( 115 ) may be placed on a conductive layer ( 100 ) such that an active surface of circuit device ( 115 ) is between conductive layer ( 100 ) and an opposite surface of circuit device ( 115 ). The conductive layer ( 100 ) has at least one opening ( 128 ) to expose the active surface of circuit device ( 115 ). The encapsulant ( 24, 126,326 ) may be electrically conductive or electrically non-conductive.
122 citations
Authors
Showing all 7673 results
Name | H-index | Papers | Citations |
---|---|---|---|
David Blaauw | 87 | 750 | 29855 |
Krishnendu Chakrabarty | 79 | 996 | 27583 |
Rajesh Gupta | 78 | 936 | 24158 |
Philippe Renaud | 77 | 773 | 26868 |
Min Zhao | 71 | 547 | 24549 |
Gary L. Miller | 63 | 306 | 13010 |
Paul S. Ho | 60 | 475 | 13444 |
Ravi Subrahmanyan | 59 | 353 | 14244 |
Jing Shi | 53 | 222 | 10098 |
A. Alec Talin | 52 | 311 | 12981 |
Chi Hou Chan | 48 | 511 | 9504 |
Lin Shao | 48 | 380 | 12737 |
Johan Åkerman | 48 | 306 | 9814 |
Philip J. Tobin | 47 | 186 | 6502 |
Alexander A. Demkov | 47 | 331 | 7926 |