Institution
Freescale Semiconductor
About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..
Topics: Layer (electronics), Signal, Transistor, Integrated circuit, Amplifier
Papers published on a yearly basis
Papers
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07 Sep 2004TL;DR: In this article, a strobe decoder function is configured to decode a plurality of different strobe signals to differentiate between triggering sub-systems on receiving devices, based on the pulse width or voltage magnitude characteristics of the respective signals.
Abstract: An apparatus (100) comprises a number of sub-systems (110, 120) and a control interface (105) operably coupled to sub-systems (110, 120) for routeing data therebetween. A strobe generation function (225, 325) is operably coupled to the control interface (105) and configured to generate a plurality of different strobe signals to differentiate between different intended receiving devices. Thus, different strobe signals may be multiplexed onto a single control interface link, based on a pulse width or voltage magnitude characteristics of the respective strobe signals. A strobe decoder function is operably coupled to the control interface (105) and configured to decode a plurality of different strobe signals to differentiate between triggering sub-systems on receiving devices.
36 citations
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21 Jan 2005TL;DR: In this paper, an autonomous memory checker is used for runtime security assurance of an electronic device, consisting of a controller, a memory reference file coupled to the controller, and an authentication engine coupled with the controller.
Abstract: Methods and apparatus are provided for an electronic device having an autonomous memory checker for runtime security assurance. The autonomous memory checker comprises a controller, a memory reference file coupled to the controller, and an authentication engine coupled to the controller. A check is performed during runtime operation of the electronic device. The autonomous memory checker generates runtime reference values corresponding to trusted information stored in memory. The runtime reference values are compared against memory reference values stored in the memory reference file. The memory reference values are generated from the trusted information stored in memory. An error signal is generated when the runtime reference values are not identical to the memory reference values thereby indicating that the trusted information has been modified.
36 citations
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26 Oct 2012TL;DR: In this article, a method of forming a semiconductor device includes forming a gate layer over a substrate in the NVM region and the logic region, forming an opening in the first gate layer, forming a charge storage layer in the opening, and replacing the first patterned gate layer portion with a logic gate comprising metal.
Abstract: A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal.
36 citations
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05 Jun 2009TL;DR: In this article, a cross-coupled inverter is coupled to an SRAM bitcell, where a first inverter of the pair includes a first device having a body and a second inverter includes a second device with a body.
Abstract: A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first input coupled to a first supply voltage terminal, a second input coupled to a second supply voltage terminal, and an output coupled to a first current electrode of the first device and to a first current electrode of the second device. A second selection circuit has a first input coupled to the first supply voltage terminal, a second input coupled to the second supply voltage terminal, and an output coupled to the body of each of the first and second devices. A word line coupled to the SRAM bitcell is driven by a word line driver coupled to the first supply voltage terminal.
36 citations
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08 Dec 1997TL;DR: In this article, a process of patterning magnetic multilayer films is described, including the steps of successively depositing a plurality of magnetic multi-layer films on a supporting substrate, selectively removing portions of the plurality using a reactive plasma etch including chlorine gas, and passivating in situ, or an adjacent evacuated chamber.
Abstract: A process of patterning magnetic multilayer films including the steps of successively depositing a plurality of magnetic multilayer films on a supporting substrate, selectively removing portions of the plurality of magnetic multilayer films using a reactive plasma etch including chlorine gas, and passivating in situ, or an adjacent evacuated chamber, remaining portions of the plurality of magnetic multilayer films, i.e. the memory elements, in a post-etch fluorinated plasma.
36 citations
Authors
Showing all 7673 results
Name | H-index | Papers | Citations |
---|---|---|---|
David Blaauw | 87 | 750 | 29855 |
Krishnendu Chakrabarty | 79 | 996 | 27583 |
Rajesh Gupta | 78 | 936 | 24158 |
Philippe Renaud | 77 | 773 | 26868 |
Min Zhao | 71 | 547 | 24549 |
Gary L. Miller | 63 | 306 | 13010 |
Paul S. Ho | 60 | 475 | 13444 |
Ravi Subrahmanyan | 59 | 353 | 14244 |
Jing Shi | 53 | 222 | 10098 |
A. Alec Talin | 52 | 311 | 12981 |
Chi Hou Chan | 48 | 511 | 9504 |
Lin Shao | 48 | 380 | 12737 |
Johan Åkerman | 48 | 306 | 9814 |
Philip J. Tobin | 47 | 186 | 6502 |
Alexander A. Demkov | 47 | 331 | 7926 |