Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Magnetic tunnel junction structure and method

Abstract: Methods and apparatus are provided for magnetic tunnel junctions (MTJs) (10, 50) employing synthetic antiferromagnet (SAF) free layers (14, 14'). The MTJ (10, 50) comprises a pinned ferromagnetic (FM) layer (32, 18), the SAF (14) and a tunneling barrier (16) therebetween. The SAF (14) has a first higher spin polarization FM layer (30) proximate the tunneling barrier (16) and a second FM layer (26) desirably separated from the first FM layer (30) by a coupling layer (28), with magnetostriction adapted to compensate the magnetostriction of the first FM layer (30). Such compensation reduces the net magnetostriction of the SAF (14) to near zero even with high spin polarization proximate the tunneling barrier (16). Higher magnetoresistance ratios (MRs) are obtained without adverse affect on other MTJ (10, 50) properties. NiFe combinations are desirable for the first (30) and second (26) free FM layers, with more Fe in the first (30) free layer and less Fe in the second (26) free layer. CoFeB and NiFeCo are also useful in the free layers.

Low-noise amplifier

Abstract: Methods and corresponding systems in a low noise amplifier include selecting a selected sub-band for amplifying, wherein the selected sub-band is one of a plurality of sub-bands, wherein each sub-band is a portion of a frequency band, and wherein each sub-band has a corresponding sub-band center frequency. Next, a gate-source capacitor is adjusted so that a real part of an LNA input impedance corresponds to a real part of a source impedance at the selected sub-band center frequency. A match capacitor is also adjusted so that the LNA input impedance corresponds to the complex conjugate of the source impedance at the selected sub-band center frequency. The gate-source capacitor and the match capacitor can each be adjusted by recalling capacitor values from memory that correspond to the selected sub-band, and connecting selected capacitor components in response to the recalled capacitor values.

Method for single sided polishing of a semiconductor wafer

Abstract: A method for polishing a single side of a semiconductor wafer (31) is disclosed for improving wafer flatness. A protective layer (32) is formed on one side of the semiconductor wafer (31). The semiconductor wafer (31) is polished on both sides concurrently using double sided polishing equipment (38,41). The protective layer (32) prevents a surface (37) of the semiconductor wafer (31) from being polished while the other unprotected surface (36) is polished thereby producing a single sided polished wafer.

Coverage metrics for verification of concurrent SystemC designs using mutation testing

Abstract: Design verification has grown to dominate the cost of electronic system design; however, designs continue to be released with latent bugs. A verification test suite developed for a sequential program is not adequate for a concurrent program. A major problem with design verification of concurrent systems is the lack of good coverage metrics. Coverage metrics are heuristic measures of the exhaustiveness of a test suite. High coverage, in general, implies fewer bugs. SystemC is the most popular concurrent system level modeling language used for designing SoCs in the industry. We propose to attack the verification quality problem for concurrent SystemC programs by developing novel mutation testing based coverage metrics. Mutation testing has successfully been applied in software testing and RTL designs. In this paper, we develop a comprehensive set of mutation operators for concurrency constructs in SystemC. Our approach is also unique in that we define a novel concurrent coverage metric considering multiple execution schedules that a concurrent program can generate. This metric allows us to adequately measure the coverage for concurrent programs. We performed experiments with various designs including a large industrial design and obtained favorable results on multiple applications.

Minimum memory operating voltage technique

Abstract: A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.