Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

AGC with integrated wideband interferer detection

Abstract: An automatic gain control (AGC) system for a receiver and corresponding method facilitate AGC in a receiver. The AGC system includes an on-channel detector (123) configured to provide an on-channel automatic gain control (AGC) indication; an off-channel signal detector (145) configured to provide an off-channel AGC indication; and a controller (143, 173) coupled to the on-channel AGC indication and the off-channel AGC indication and configured to provide a gain control signal corresponding to at least one of the on-channel AGC indication and the off-channel AGC indication.

Method and apparatus for dynamic prefetch buffer configuration and replacement

Abstract: A memory controller (32) and method thereof configures a prefetch buffer (30) dynamically for interfacing between multiple bus masters (12, 14, 16) of different burst support and multiple memories having different characteristics. A line size of at least a portion of the prefetch buffer (30) is modified based upon the memory controller receiving a read request from one of the bus masters (12, 14, 16). An adaptive method to optimally replace prefetch buffer lines uses prioritized status (status) field information to determine which buffer line to replace.

Recording of result information in a built-in self-test circuit and method therefor

Abstract: An integrated circuit has a Built-In Self-Test (BIST) controller ( 10 ) that has a sequencer ( 16 ) that provides test algorithm information for multiple memories ( 44, 46, 48, 50 ). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces ( 32, 34, 36, 38 ) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. When test algorithms fail or complete execution, pertinent BIST information is stored in non-user addressable space of the multiple memories.

Method for forming a semiconductor device and structure thereof

Abstract: A non-planar semiconductor device (10) starts with a silicon fin (42). A source of germanium (e.g. 24, 26, 28, 30, 32) is provided to the fin (42). Some embodiments may use deposition to provide germanium; some embodiments may use ion implantation (30) to provide germanium; other methods may also be used to provide germanium. The fin (42) is then oxidized to form a silicon germanium channel region in the fin (36). In some embodiments, the entire fin (42) is transformed from silicon to silicon germanium. One or more fins (36) may be used to form a non-planar semiconductor device, such as, for example, a FINFET, MIGFET, Tri-gate transistor, or multi-gate transistor.

Data processing method, data processor and apparatus including a data processor

Abstract: A method of processing data in a data processor comprising at least two data processing units. The method comprises performing different data processing steps in the data processing units concurrently during a parallel operation (405), and replicating performances of selected identical data processing steps in the data processing units during a non-synchronised redundant operation (401 ). The non-synchronised redundant operation (401 ) comprises an initial performance (402) of the selected identical data processing steps in one of the data processing units and a replicate performance (404) of the data processing steps starting later than the initial performance (402), preferably in another of the data processing units. Initial result data representative of results from the initial performance are registered (412, 414), and compared (434) with replicate result data representative of results from the replicate performance (404), and an error signal (434) is produced in case of discrepancy.