Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Sensor having free fall self-test capability and method therefor

Abstract: A transducer (20) includes a movable element (24), a self-test actuator (22), and a sensing element (56, 58). The sensing element (56, 58) detects movement of the movable element (24) from a first position (96) to a second position (102) along an axis perpendicular to a plane of the sensing element (56, 58). The second position (102) results in an output signal (82) that simulates a free fall condition. A method (92) for testing a protection feature of a device (70) having the transducer (20) entails moving the movable element (24) to the first position (102) to produce a negative gravitational force detectable at the sensing element (56, 68), applying a signal (88) to the actuator (22) to move the movable element (24) to the second position (102) by the electrostatic force (100) , and ascertaining an enablement of the protection feature in response to the simulated free fall.

Design verification system for avoiding false failures and method therefor

Abstract: Embodiments of the present invention provide for a method and system for verifying that an implementation design is functionally equivalent to a predetermined functionality of a reference design where the reference and implementation designs may correspond to a portion of a larger integrated circuit design. The use of Symbolic Trajectory Evaluation (STE) to compare the designs may result in false failures. Therefore, one aspect of the present invention provides for comparing an expected result from the reference design to an actual result of the implementation design in order to determine a set of failure conditions. Constraints are then selectively applied to the set of failure conditions in an attempt to remove them. Another aspect of the present invention allows for the selective use of symbols rather than “X”s (unknowns) in order to avoid false failures due to certain inputs of the implementation design not being properly stimulated.

Software Standards for the Multicore Era

Abstract: Systems architects commonly use multiple cores to improve system performance. Unfortunately, multicore hardware is evolving faster than software technologies. New multicore software standards are necessary in light of the new challenges and capabilities that embedded multicore systems provide. The newly released multicore communications API standard targets small-footprint, highly efficient intercore and interchip communications.

Performance and Variability Comparisons between Multi-Gate FETs and Planar SOI Transistors

Abstract: This paper compares the performance and inter-die variability of doped and undoped channel Multiple-Gate FETs (MUGFETs) with respect to planar SOI devices. We show that doped-channel FinFETs have equivalent variability to narrow-width planar devices. As such, transitions to FinFETs for narrow-width devices will likely incur minimal variability impact. To match the low variability of wide-width planar devices, conversions to undoped channel FinFETs will be necessary. Furthermore, good short-channel control has to be maintained since undoped channel devices exhibit increase sensitivity to Tbody relative to doped channel FinFETs due to enhanced fully-depleted channel electrostatics.

Modeling and Analysis of Parasitic Resistance in Double-Gate FinFETs

Abstract: A comprehensive model is presented to analyze the three-dimensional (3-D) source-drain (S/D) resistance of undoped double-gated FinFETs of wide and narrow S/D width. The model incorporates the contribution of spreading, sheet, and contact resistances. The spreading resistance is modeled using a standard two-dimensional (2-D) model generalized to 3-D. The contact resistance is modeled by generalizing the one-dimensional (1-D) transmission line model to 2-D and 3-D with appropriate boundary conditions. The model is compared with the S/D resistance determined from 3-D device simulations and experimental data. We show excellent agreement between our model, the simulations, and experimental data.