Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

The Redistributed Chip Package: A Breakthrough for Advanced Packaging

Abstract: The redistributed chip package (RCP) is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wirebond BGA and flip chip BGA packaging. Devices are encapsulated into panels while routing of signals, power, and ground is built directly on the panel. The RCP panel and signal build-up lowers the cost of the package by eliminating wafer bumping and substrates thereby enabling large scale assembly in panel form. The build-up provides better routing capabilities and better integration. Also, by eliminating bumping, the device interconnect is inherently Pb-free, and the stress of the package is reduced enabling ultra-low K device compatibility. The panel is created by attaching device active side down to a substrate, encapsulating and curing the devices, grinding to desired thickness, and then removing the substrate. Signal, power, and ground planes are created using redistribution-like processing. Multi-layer metal RCP packages have passed -40 to 125C air-to-air thermal cycling and HAST after MSL3/260 preconditioning.

Integrated circuit device and method for determining an index of an extreme value within an array of values

Abstract: An integrated circuit device comprises at least one digital signal processor, DSP, module, the at least one DSP module comprising a plurality of data registers and at least one data execution unit, DEU, module arranged to execute operations on data stored within the data registers. The at least one DEU module is arranged to, in response to receiving an extreme value index instruction, compare a previous extreme value located within a first data register set of the DSP module with at least one input vector data value located within a second data register set of the DSP module, and determine an extreme value thereof. The at least one DEU module is further arranged to, if the determined extreme value comprises an input vector data value located within the second data register set, store the determined extreme value in the first data register set, determine an index value for the determined extreme value, and store the determined index value in the first data register set.

A direct-conversion receiver for DVB-H

Abstract: A fully integrated low-power ultrahigh-frequency (UHF) tuner integrated circuit (IC) design for the digital video broadcasting-handheld (DVB-H) market is presented. A direct-conversion receiver is chosen over classical digital video broadcasting-terrestrial (DVB-T) architectures. The tuner IC covers UHF bands IV/V. The solution is based on a radio frequency integrated circuit (RFIC) and external low-noise amplifier (LNA) to meet the noise figure (NF) specification of 5 dB, IIP3 of 4dBm, and Gain of 89 dB. The IC includes an LNA, dual quadrature mixers, multiple bandwidth baseband (BB) filtering, three 4X voltage-controlled oscillators (VCOs), integer phase-locked loop (PLL), and reference oscillator. The design is implemented in a SiGe:C bipolar complementary metal oxide semiconductor (BiCMOS) technology and the die area is 11.5 mm/sup 2/.

Sloped contact etch process

Abstract: The process described provides a sloped contact etch The process has the steps of: etching a substrate 12 then removing the polymer that is produced during the substrate 12 etch These two steps are alternated until a desired depth is reached Next, the resist 11 is etched followed by an etch of the substrate 12 This is then repeated until the required depth is reached By varying the duration and repetition of the etches, the slope of the etch can be regulated

Method for forming a transistor having silicided regions

Abstract: A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.