Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Method and apparatus for providing structural support for interconnect pad while allowing signal conductance

Abstract: A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.

Method for generating an optimized integrated circuit cell library

Abstract: A cell library (21) is optimized for specific operating characteristics. A stimulus file (23) is divided into a number of simulation run files. The simulation run files (27) are distributed to more than one computer work station so that the simulation of the cell occurs in parallel. The netlist (24) of each cell is parameterized to allow the cell to be changed and resimulated to better meet the specific operating characteristics. A cost function (32) is provided which uses the results of a transistor level simulation to calculate the quality of the cell design relative to the specific operating characteristics. Simulated annealing (34) is used to generate new simulation parameter values from a cost generated from the cost function (32). The cell is resimulated a number of times to optimize for the specific operating characteristics and the best design is retained for a new cell library (39). The process is repeated for each cell of the cell library (21).

Process for etching tapered polyimide vias

Abstract: A polyimide-oxide-polyimide integrated circuit structure is utilized in the process for forming openings having tapered sidewalls and predetermined controlled sizes. At least one opening size is replicated and transferred to an exposed surface in a underlying surface of the structure by first forming a thick layer of oxide over the first cured polyimide layer, anisotropically etching the thick layer of oxide to form an opening of predetermined size therethrough to the surface of the first cured polyimide layer. Next, the first layer of cured polyimide is isotropically etched to form an opening therethrough of substantially said predetermined size and exposing a portion of a thin layer of oxide underlying the first layer of cured polyimide. The thin layer of oxide is then anisotropically etched using the thick layer of oxide as an etch mask to expose an opening of said predetermined size on a surface of a second layer of cured polyimide. The second layer of cured polyimide is then anisotropically etched again using the thick layer of oxide as the etch mask to transfer and replicate the opening in the thick layer onto the surface of the underlying region. Thereafter the thick layer of oxide is removed. Metalization can then be deposited on the resulting structure to make contact to the underlying surface.

Method of aligning and mounting an electronic device on a printed circuit board using a flexible substrate having fixed lead arrays thereon

Abstract: An electronic component having a flexible substrate with conductive traces thereon may have the leads separated into arrays that are shaped to contact and be surface mounted to the bonding lands on a printed circuit board (PCB). The flexible substrate, such as polyimide, adheres to the traces and is formed into lead arrays with them. The lead arrays thus keep portions of the leads and the outer bonding areas corresponding thereto aligned with respect to each other during handling and mounting to the PCB. An alignment mechanism may be optionally present on the lead arrays that mates with a corresponding mechanism on the PCB. The package body itself may be overmolded, assembled from prior parts, etc. Another alternative version includes test points on the perimeter of the substrate beyond the outer bonding areas that may be used to test the device, such as an integrated circuit chip or die, at an intermediate stage in the assembly process. The periphery and test points may be sheared away before the package is mounted to the PCB. A variety of outer bonding area pitches may be provided on the same package with test points of a standard pitch. The relatively inexpensive device is thin and easily mounted by conventional techniques.

Method and apparatus for controlling a data processing system during debug

Abstract: A data processing system (10) includes a debug unit (14) that is capable of providing unobtrusive debug capabilities to the normal operation of the data processing system by controlling activation of all or a selected subset of a plurality of subsystems as needed for a debug operation. For example, power can be conserved by activating selected subsystems as needed for a debug operation. Furthermore, in one embodiment, the debug unit provides a level of activation, ranging from deactivation to full activation, to the selected subsystems which provides further control of the data processing system. In one embodiment, debug control and status registers (40) are provided for power management handshaking between the debug unit and the plurality of subsystems. The handshaking can be used to ensure that a debug operation may proceed properly since the selected subsystems are capable of providing status information to the debug unit.