Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Method for forming a transistor having silicided regions

Abstract: A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.

Closed loop current control circuit and method thereof

Abstract: A circuit and method for providing closed loop control using constant current switching techniques is disclosed herein. By controlling the current supplied to high intensity light emitting diodes (LEDs) using the techniques and circuits described, high intensity LEDs can be operated at or near their maximum capacity without danger of overloading the LEDs, and without using excess amounts of current. A circuit as described herein, has multiple high side switches, each of which is connected to an LED array. The LED arrays are in turn connected through an inductor to a current switching control section that switches current to ground, or recirculates the current to maintain LED current flow within a desired range.

Area-array device assembly with pre-applied underfill layers on printed wiring board

Abstract: The invention provides a method of attaching an area-array device such as a bumped flip chip to an electrical substrate. An underfill material is applied to a portion of the electrical substrate, and the underfill material is heated to an underfill-material staging temperature. A bumped area-array device is provided, the bumped area-array device including an interconnection surface and a plurality of connective bumps extending from the interconnection surface. The interconnection surface of the bumped area-array device is positioned adjacent the applied underfill material. The bumped area-array device is heated to electrically connect the connective bumps to the electrical substrate. The invention also provides a flip-chip assembly and a printed wiring board panel with pre-applied underfill material.

Integrated image reject mixer

Abstract: An integrated image reject mixer (150) generates precise quadrature components using highly matched local-oscillator (LO) path and intermediate frequency (IF) path resistor-capacitor (RC) phase shifting networks (131, 138). Because the LO signal from a local oscillator (127) has a constant amplitude, a phase detector (136) feedback loop easily maintains an accurate ninety-degree phase difference between the quadrature LO signals (122, 124) from the LO path phase shifting network (131). Because the two phase shifting networks are matched, the feedback control signal (137) from the phase detector (136) can also be used to maintain an accurate ninety-degree phase difference between the quadrature IF signals (123, 128) from the IF path phase shifting network (138) despite the dynamically-varying amplitude of the IF signal. Thus, this image reject mixer uses only components that may be easily integrated into an integrated circuit.

Differential DC offset compensation circuit

Abstract: A differential direct current (DC) offset compensation circuit for providing DC offset compensation to a circuit device (110). The DC offset compensation circuit (100) comprises a differential integrator (120) and a summing network (130). The circuit device (110) is one of several types of devices, such as a DC coupled amplifier. The differential input (112) of the circuit device (110) is suitable for coupling to a differential input source (140) and the differential output (114) of the circuit device is suitable for connection to a load (150). The differential integrator (120) features a transconductance amplifier (18) at least one other amplifier (13), and a capacitor element (16) having a capacitance of C1. The summing network (130) sums the differential integrator output with the differential input signals of the differential input source (140) and cancels DC offsets of the differential input source (140) and the circuit device (110).