Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

A cost effective 32nm high-K/ metal gate CMOS technology for low power applications with single-metal/gate-first process

Abstract: For the first time, we have demonstrated a 32 nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 mum2. Record NMOS/PMOS drive currents of 1000/575 muA/mum, respectively, have been achieved at 1 nA/mum off-current and 1.1 V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0 V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at Lgate = 30 nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements.

Redundancy for a block-architecture memory

Abstract: A block architecture memory has two stacks of memory blocks. Between the two stacks are blocks of sense amplifiers. Each block of sense amplifiers is coupled to a memory block in each of the stacks of memory blocks via local data lines. Located at the bottom of each stack of memory blocks is a redundant block of columns of memory cells. There is a redundant sense amplifier located between and coupled to the redundant blocks of columns via local data lines. The redundant sense amplifier is also coupled to a redundant global data line. An input/output multiplexer is coupled to all of the global data lines. The multiplexer provides and receives external data. If one of the redundant columns is to replace a defective column for a particular address, then the redundant global data line carries data which corresponds to the external data.

Method of operating a media access controller

Abstract: A method is provided for a remote device to monitor and communicate with a wireless network using cyclic beacons. The remote device receives a beacon (1405), which beacon includes beacon information that defines a superframe. From the beacon information, the remote device determines whether the received beacon and the associated superframe are assigned to a network device or are unassigned (1410). By receiving as many beacons as there are allowable devices in the network, the remote device can determine if the network is full (1430). If the remote device runs through all of the beacons and all indicate that their associated superframes are assigned, then the remote device determines that the network is full and performs a network-full function. If the remote device receives a beacon that indicates that its associated superframe is unassigned, it determines that the network is not full and performs an association request during the unassigned superframe (1415).

Method for forming pitch independent contacts and a semiconductor device having the same

Abstract: A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.

Electrostatic discharge protection circuitry and method of operation

Abstract: An Electrostatic Discharge (ESD) protection circuit (9) includes a plurality of I/O and power supply pad cells (22, 40) that comprise external pads (31, 41) and circuitry requiring ESD protection. The protection circuit includes an array of shunting devices (36, 46) coupled in parallel between an ESD bus (14) and a VSS bus (18) and distributed among the plurality of pad cells. One or more trigger circuits (50) control the shunting devices. ESD events are coupled from any stressed pad onto two separate buses: the ESD bus which routes the high ESD currents to the positive current electrodes of the multiple shunting devices, and a Boost bus (12) which controls the trigger circuits. During an ESD event, the trigger circuits drive the control electrodes of the shunting devices to a voltage level greater than possible with prior art circuits, thereby reducing the on-resistance of the shunting devices.