Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Electronic component and method of packaging

Abstract: A method of packaging an electronic component includes forming a hole (24) in a substrate (21) having a first surface (22) opposite a second surface (23) and disposing and patterning a malleable layer (26) over the first surface (22) and over the hole (24) of the substrate (21). The malleable layer (26) has a third surface (27) opposite a fourth surface (28). A portion (29) of the fourth surface (28) is exposed by the hole (24) in the substrate (21). An electrically conductive layer is simultaneously disposed over the portion (29) of the fourth surface (28) and over a different portion of the third surface (27) of the malleable layer (26). The malleable layer (26) is deformed into the hole (24). Then, a semiconductor die (43) is coupled to the malleable layer (26), and an underencapsulant (37) is disposed under the semiconductor die (43) and over the hole (24).

Method for manufacturing a high dielectric constant gate oxide for use in semiconductor integrated circuits

Abstract: A method for forming a gate dielectric (14b) begins by providing a substrate (12). A high K dielectric layer (14a) is deposited overlying the substrate (12). The dielectric layer (14a) contains bulk traps (16) and interface traps (18). A polysilicon gate electrode (20) is then patterned and etched overlying the gate dielectric (14a) whereby the plasma etching of the gate electrode (20) results in substrate plasma damage (22). A post gate wet oxidation process is performed between 750° C. and 850° C. to reduce plasma etch damage and trap sites (16, 18) in order to provide an improved gate dielectric (14b). Source and drain electrodes (30) are then formed within the substrate and laterally adjacent the gate electrode (20) to form a transistor device having more consistent threshold voltages, improved subthreshold slope operation, reduced gate to channel leakage, and improved speed of operation.

Frequency and Power Correlation between At-Speed Scan and Functional Tests

Abstract: At-speed scan is a key technique in modern IC testing. One of its drawbacks, with respect to functional tests, is its excessive power consumption leading to voltage drop and frequency degradation. This paper discusses the frequency and power correlation between At-speed scan and functional tests. The influence of voltage drop on frequency is demonstrated by silicon measurements and supporting simulation results. The localized nature of the voltage drop as well as impedance component analysis are presented. Additionally, the need for power aware scan patterns is also discussed. Suggestions for achieving a higher correlation between At-speed scan and functional patterns, with respect to power consumption, are offered.

One transistor dram cell structure and method for forming

Abstract: A one-transistor dynamic random access memory (DRAM) cell includes a transistor (10) which has a first source/drain region (26) a second source/drain region (24), a body region (36) between the first and second source/drain regions, and a gate (28) over the body region. The first source/drain region includes a Schottky diode junction with the body region and the second source/drain region includes an n-p diode junction with the body region.

Electron optics for multi-beam electron beam lithography tool

Abstract: A charge particle optical column capable of being used in a high throughput, mutli-column, multi-beam electron beam lithography system is disclosed herein. The column has the following properties: purely electrostatic components; small column footprint (20 mm square); multiple, individually focused charge particle beams; telecentric scanning of all beams simultaneously on a wafer for increased depth of field; and conjugate blanking of the charged particle beams for reduced beam blur. An electron gun is disclosed that uses microfabricated field emission sources and a microfabricated aperture-deflector assembly. The aperture-deflector assembly acts as a perfect lens in focusing, steering and blanking a multipicity of electron beams through the back focal plane of an immersion lens located at the bottom of the column. Beam blanking can be performed using a gating signal to decrease beam blur during writing on the wafer.