Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Means for stabilizing polycrystalline semiconductor layers

Abstract: Implantation of oxygen or nitrogen in polysilicon layers to a dose above about 10 15 ions/cm 2 retards rapid grain boundary migration of conventional dopants such as B, P, As, Sb, and the like during dopant activation. Pre-annealing of the poly films to increase the grain size also decreases rapid grain boundary migration. The effects can be combined by first pre-annealing and then implanting oxygen or nitrogen before introducing the dopant. It is desirable to anneal the oxygen implant before introducing the dopant to allow for oxygen diffusion to the grain surfaces where it precipitates and blocks the grain boundaries. Vertical and lateral migration of the dopants can be inhibited by placing the implanted oxygen or nitrogen between the dopant and the location desired to be kept comparatively free of dopants. When very high dopant activation temperatures are used the blocking effect of the oxygen on the grain boundaries is overwhelmed by dopant diffusion through the grains.

Multiple integrated circuit module which simplifies handling and testing

Abstract: A multi-chip module (26) used to interconnect and house a plurality of integrated circuits (10). The module (26) employs an intermediate structure referred to, herein, as a bridge chip (12). The bridge chip (12) connects the integrated circuit (10) to the module substrate (19). The integrated circuit (10) is attached to the bridge chip (12) and forms a composite structure (18) which can be burned-in and tested as an individual unit. The bridge chip (12) has interconnects to bring out the inputs and outputs of the integrated circuit (10). The composite structure (18) is mounted to the module substrate (19) such that, the integrated circuit (10) has a thermal pathway to the module substrate (19), and the bridge chip (12) connects to the module substrate (19). The module substrate (19) has interconnects to connect the plurality of composite structures (18).

Characterizing and comparing prevailing simulation techniques

Abstract: Due to the simulation time of the reference input set, architects often use alternative simulation techniques. Although these alternatives reduce the simulation time, what has not been evaluated is their accuracy relative to the reference input set, and with respect to each other. To rectify this deficiency, this paper uses three methods to characterize the reduced input set, truncated execution, and sampling simulation techniques while also examining their speed versus accuracy trade-off and configuration dependence. Finally, to illustrate the effect that a technique could have on the apparent speedup results, we quantify the speedups obtained with two processor enhancements. The results show that: 1) the accuracy of the truncated execution techniques was poor for all three characterization methods and for both enhancements, 2) the characteristics of the reduced input sets are not reference-like, and 3) SimPoint and SMARTS, the two sampling techniques, are extremely accurate and have the best speed versus accuracy trade-offs. Finally, this paper presents a decision tree which can help architects choose the most appropriate technique for their simulations.

No-chip debug peripheral which uses externally provided instructions to control a core processing unit

Abstract: A data processing system having a debug peripheral is provided. The debug peripheral is coupled to a central processing unit and memory via an internal communications bus. The debug peripheral is a single-word dual port memory with parallel read-write write access on one side, and synchronous, full-duplex serial read-write access on the other side. The serial side of the debug peripheral is connected to external emulation hardware by means of a three-pin synchronous serial interface. The parallel access is via a connection to a core central processing unit (CPU) internal communications bus. The debug peripheral is addressed at sixteen adjacent locations in the CPU memory space. During a debug interlude, the debug peripheral assumes control of the CPU by providing an interrup signal to the CPU, and thereby causing the CPU to fetch instructions directly from the debug peripheral. The debug peripheral receives instructions from the external emulation hardware, and provides the debug instructions to the CPU, in response to an instruction address provided by the CPU.

Method of routing an integrated circuit

Abstract: A method for automatically selecting tie styles used during the horizontal placement of substrate and well ties. A linear order of tie styles is determined (2422). Ties are placed horizontally in the layout based upon an initial tie style (2424). Route and compact layout components (2426). If the layout has satisfied the tie coverage rules (2428) the tie style selection process is complete. Otherwise, contacts, vias and ties are added where possible (2430). If the layout has now satisfied the tie coverage rules (2432) tie style selection process is complete. If not, the next tie style is chosen from the linear order (2434). The process continues by placing (2424), routing and compacting components (2426) with the new tie style, until the cell satisfies the tie coverage rules.