Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Vertically integrated MEMS sensor device with multi-stimulus sensing

Abstract: A microelectromechanical systems (MEMS) sensor device ( 184 ) includes a sensor portion ( 180 ) and a sensor portion ( 182 ) that are coupled together to form a vertically integrated configuration having a hermetically sealed chamber ( 270 ) The sensor portions ( 180, 182 ) can be formed utilizing different micromachining techniques, and are subsequently coupled utilizing a wafer bonding technique to form the sensor device ( 184 ) The sensor portion ( 180 ) includes one or more sensors ( 186, 188 ), and the sensor portion ( 182 ) includes one or more sensors ( 236, 238 ) The sensors ( 186, 188 ) are located inside the chamber ( 270 ) facing the sensors ( 236, 238 ) also located inside the chamber ( 270 ) The sensors ( 186, 188, 236, 238 ) are configured to sense different physical stimuli, such as motion, pressure, and magnetic field

Electro-optic structure and process for fabricating same

Abstract: High quality epitaxial layers of oxide can be grown overlying large silicon wafers (22) by first growing an accommodating buffer layer (26) on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (24) of silicon oxide. The amorphous intermediate layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous intermediate layer. Waveguides (45) may be formed of high quality monocrystalline material atop the monocrystalline buffer layer. The waveguides can suitably be formed to modulate the wave. Monolithic integration of oxide based electro-optic devices with III-V based photonics and Si circuitry is fully realized.

Challenges for 3D IC integration: bonding quality and thermal management

Abstract: In this contribution, two main challenges for wafer-to wafer 3D integration are investigated: bonding quality (including wafer-to-wafer alignment) and thermal management. The bonding process considered in this study is direct SiO2/SiO2 hydrophilic bonding. It is shown that, after process optimization, lower than 1.5 mum misalignment was achieved without significant bonding defects. In a second part, a 3D thermal modeling was done to estimate the temperature increase in a two-stratum 3D integration. Local (3D) and global (ID) modeling contribution to the maximum temperature are discussed. It is shown that, thermal resistance due to local 3D effects can be higher than ID thermal resistance. However, thermal effects seem to be manageable.

Die encapsulation using a porous carrier

Abstract: A process for encapsulating an integrated circuit die (403) using a porous carrier (101). In one example, an adhesive structure (e.g. tape) is applied to a porous carrier. Integrated circuit die is then placed on the adhesive structure. The integrated circuit die is then encapsulated to form an encapsulated structure (505). The carrier is then subjected to a solvent that passes through the carrier to reduce the adhesive strength of the adhesive structure for removal of the carrier from the encapsulated structure.

Simulation of computer architectures: simulators, benchmarks, methodologies, and recommendations

Abstract: Simulators have become an integral part of the computer architecture research and design process. Since they have the advantages of cost, time, and flexibility, architects use them to guide design space exploration and to quantify the efficacy of an enhancement. However, long simulation times and poor accuracy limit their effectiveness. To reduce the simulation time, architects have proposed several techniques that increase the simulation speed or throughput. To increase the accuracy, architects try to minimize the amount of error in their simulators and have proposed adding statistical rigor to their simulation methodology. Since a wide range of approaches exist and since many of them overlap, this paper describes, classifies, and compares them to aid the computer architect in selecting the most appropriate one.