Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Method for forming a semiconductor device having a mechanically robust pad interface.

Abstract: A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad ( 134 ) that is formed over a semiconductor substrate ( 100 ). A dielectric layer ( 136 ) is then formed over the conductive bond pad ( 134 ). Portions of the dielectric layer ( 136 ) are removed such that the dielectric layer ( 136 ) becomes perforated and a portion of the conductive bond pad ( 134 ) is exposed. Remaining portions of the dielectric layer ( 136 ) form support structures ( 138 ) that overlie that bond pad. A self-passivating conductive capping layer ( 204 ) is then formed overlying the bond pad structure, where the perforations in the dielectric layer ( 136 ) allow for electrical contact between the capping layer ( 204 ) and the exposed portions of the underlying bond pad ( 134 ). The support structures ( 138 ) provide a mechanical barrier that protects the interface between the capping layer ( 204 ) and the bond pad ( 134 ). Additional mechanical robustness is achieved when the support structures ( 138 ) remain coupled to the unremoved portion of the dielectric layer ( 136 ), as forces buffered by the support structures ( 138 ) are distributed across the dielectric layer ( 136 ) and not concentrated at the bond pad location.

Integrated impedance matching and stability network

Abstract: An integrated circuit for intermediate impedance matching and stabilization of high power devices is disclosed. High quality epitaxial layers of monocrystalline materials grown over monocrystalline substrates enables the formation of impedance matching and stability circuits to be placed on the same substrate as the active device. Additionally, by using the manifolds of the active to form plates of a capacitor, an impedance matching network of series inductance and shunt capacitor can be compactly fabricated for increasing the output impedance to intermediate levels. The manifolds of the active device are also used to form capacitors to provide stability to high power active devices.

Capped dual metal gate transistors for CMOS process and method for making the same

Abstract: A first gate ( 120 ) and a second gate ( 122 ) are preferably PMOS and NMOS transistors, respectively, formed in an n-type well ( 104 ) and a p-type well ( 106 ) In a preferred embodiment, first gate ( 120 ) includes a first metal layer ( 110 ) of titanium nitride on a gate dielectric ( 108 ), a second metal layer ( 114 ) of tantalum silicon nitride and a silicon containing layer ( 116 ) of polysilicon Second gate ( 122 ) includes second metal layer ( 114 ) of a tantalum silicon nitride layer on the gate dielectric ( 108 ) and a silicon containing layer ( 116 ) of polysilicon First spacers ( 124 ) are formed adjacent the sidewalls of the gates to protect the metals from chemistries used to remove photoresist masks during implant steps Since the chemistries used are selective to polysilicon, the spacers ( 124 ) need not protect the polysilicon capping layers, thereby increasing the process margin of the spacer etch process The polysilicon cap also facilitates silicidation of the gates

Validation of MOSFET model Source–Drain Symmetry

Abstract: This paper presents dc and ac tests that verify whether a MOSFET model is symmetric with respect to a source-drain reversal. The tests are valid in the presence of and also verify the symmetry of gate and bulk currents, and evaluate the symmetry of all components of MOSFET charge models

Process for fabricating a silicon on insulator field effect transistor

Abstract: A process for fabricating an isolated silicon on insulator (SOI) field effect transistor (FET) (10, 11, 13, 15). The SOI FET is made on a substrate material (12). In one form, a first control electrode referred to as gate (24), is contained within the substrate (12) underlying a dielectric layer (14). A second control electrode referred to as gate (26) overlies a dielectric layer (28). A source and a drain current electrode are formed from a germanium-silicon layer (18). A silicon layer (16) forms an isolated channel region of the SOI FET. The gates (12, 24) are separated from the channel by gate dielectric layers (14, 28). The germanium-silicon layer (18) is much thicker than the silicon layer (16) which is made thin to provide a thin channel region. An optional nitride layer 20 overlies the germanium-silicon layer (18).