Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Flip-chip assembley with thin underfill and thick solder mask

Abstract: The invention provides a method for attaching a flip chip (210) to an electrical substrate (240) such as a printed wiring board. A bumped flip chip is provided, the flip chip including an active surface and a plurality of connective bumps (220) extending from the active surface, each connective bump including a side region. A thin layer of an underfill material (230) is applied to the active surface of the flip chip and to a portion of the side regions of the connective bumps. The flip chip is positioned on the electrical substrate, the electrical substrate including a thick layer of a solder mask (250) disposed on the electrical substrate. The flip chip is heated to electrically connect the flip chip to the electrical substrate, wherein the underfill material and the solder mask combine to form a stress-relief layer when the flip chip is electrically connected to the electrical substrate.

Compaction scheme in NVM

Abstract: A method of erasing a semiconductor nonvolatile memory (NVM) so as to compact the distribution of cell erased threshold voltages within a restricted range around a target erased threshold voltage. Erase pulses are applied to NVM cells until a determination is made by, for example, sensing total column source current that adequate erasure has been realized. An optional soft program signal may be applied subsequent to each erase pulse in order to impede over-erasure. Once erasure has been verified, the distribution of erased threshold voltages is compacted by sustaining, for a predetermined length of time, the simultaneous application of a gate voltage that is equal to the target erased threshold voltage and a highly positive drain voltage.

Transistor fabrication using double etch/refill process

Abstract: A semiconductor fabrication process includes forming a gate electrode ( 120 ) overlying a gate dielectric ( 110 ) overlying a semiconductor substrate ( 102 ). First spacers ( 124 ) are formed on sidewalls of the gate electrode ( 120 ). First s/d trenches ( 130 ) are formed in the substrate ( 102 ) using the gate electrode ( 120 ) and first spacers ( 124 ) as a mask. The first s/d trenches ( 130 ) are filled with a first s/d structure ( 132 ). Second spacers ( 140 ) are formed on the gate electrode ( 120 ) sidewalls adjacent the first spacers ( 124 ). Second s/d trenches ( 150 ) are formed in the substrate ( 102 ) using the gate electrode ( 120 ) and the second spacers ( 140 ) as a mask. The second s/d trenches ( 150 ) are filled with a second s/d structure ( 152 ). Filling the first and second s/d trenches ( 130, 150 ) preferably includes growing the s/d structures using an epitaxial process. The s/d structures ( 132, 152 ) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.

System and method of communicating between trusted and untrusted computer systems

Abstract: A computer network comprising a trusted computer network (16), and an untrusted computer network (17) A plurality of firewall systems (21) provide controlled access between the trusted computer network and the first untrusted computer network An Application layer bridge (22) establishes a transparent virtual circuit across the plurality of firewalls (21)

Planar ultra wide band antenna with integrated electronics

Abstract: An planar ultra wide bandwidth (UWB) antenna that provides integration of electronics is disclosed. The antenna has a first balance element that is connected to a terminal at one end. A second balance element is connected to another terminal at one end. The second balance element has a shape that mirrors the shape of the first balance element such that there is a symmetry plane where any point on the symmetry plane is equidistant to all mirror points on the first and second balance elements. Each of the balance elements is made of a generally conductive material. A triangular shaped ground element is situated between the first balance element and the second balance element with an axis of symmetry on the symmetry plane, and oriented such that the base of the triangle is towards the terminals. Accordingly, the ground element and each of the balance elements form two tapered gaps which widen and converge at the apex of the ground element as the taper extends outwardly from the terminals. Under this arrangement, sensitive UWB electronics can be housed within the perimeter of the ground element, thereby eliminating transmission line losses and dispersion, and minimizing and system ringing. A resistive loop connected between the first and second balance elements extends the low frequency response and improves the VSWR. A connection of an array of elements is disclosed that provides a low-frequency cutoff defined by the array size rather than the element size.