Institution
Freescale Semiconductor
About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..
Topics: Layer (electronics), Signal, Transistor, Integrated circuit, Amplifier
Papers published on a yearly basis
Papers
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29 Oct 2004TL;DR: In this paper, two different transistors types are made on different crystal orientations in which both are formed on SOI, and the transistors of the different types are then formed on the different resulting crystal orientation.
Abstract: Two different transistors types are made on different crystal orientations in which both are formed on SOI. A substrate has an underlying semiconductor layer of one of the crystal orientations and an overlying layer of the other crystal orientation. The underlying layer has a portion exposed on which is epitaxially grown an oxygen-doped semiconductor layer that maintains the crystalline structure of the underlying semiconductor layer. A semiconductor layer is then epitaxially grown on the oxygen-doped semiconductor layer. An oxidation step at elevated temperatures causes the oxide-doped region to separate into oxide and semiconductor regions. The oxide region is then used as an insulation layer in an SOI structure and the overlying semiconductor layer that is left is of the same crystal orientation as the underlying semiconductor layer. Transistors of the different types are formed on the different resulting crystal orientations.
84 citations
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16 Sep 1996TL;DR: In this article, a control bit in a processor status register (PSR) is used to select between a general register file and an alternate register file depending upon a logic value to which it is set to a during an exception handling process.
Abstract: A data processing system selects between a general register file and an alternate register file during an operation such that resources of the data processor may be more flexibly mapped to a context of the data processing system and, therefore, be more efficiently utilized. A control bit in a processor status register (PSR) is used to select between a general register file and an alternate register file depending upon a logic value to which it is set to a during an exception handling process.
84 citations
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04 Jun 2003TL;DR: In this article, a magnetoresistive tunneling junction memory cell (MNTJ) consisting of a pinned ferromagnetic region (17) having a magnetic moment vector (47) fixed in a preferred direction in the absence of an applied magnetic field was proposed.
Abstract: A magnetoresistive tunneling junction memory cell (10) comprising a pinned ferromagnetic region (17) having a magnetic moment vector (47) fixed in a preferred direction in the absence of an applied magnetic field wherein the pinned ferromagnetic region has a magnetic fringing field (96), an electrically insulating material positioned on the pinned ferromagnetic region to form a magnetoresistive tunneling junction (16), and a free ferromagnetic region (15) having a magnetic moment vector (53) oriented in a position parallel or anti-parallel to that of the pinned ferromagnetic region wherein the magnetic fringing field is chosen to obtain a desired switching field.
83 citations
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03 Jan 1994TL;DR: In this paper, a printed circuit board (10) comprises a polymeric coating (30) and a metal circuit trace (26) applied to a substrate (22), the coating defines an opening (32) whereat the substrate is uncoated.
Abstract: A printed circuit board (10) comprises a polymeric coating (30) and a metal circuit trace (26) applied to a substrate (22). The coating defines an opening (32) whereat the substrate is uncoated. The metal circuit trace includes a runner section (28) that is covered by the polymeric coating and a bond pad (20) integrally formed to the runner section at the opening and having an upper surface (40) that includes lip (36) overlying the polymer coating to facilitate positioning of a component for solder bonding to the pad. The bond pad preferably also includes a surface accessible within the opening to enhance solder bonding to the bond pad.
83 citations
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17 May 2000TL;DR: In this paper, a method of processing a high K gate dielectric includes growing a high quality silicon dioxide layer at the silicon interface followed by deposition of a metal layer, which is then diffused into the silicon dioxide.
Abstract: A method of processing a high K gate dielectric includes growing a high quality silicon dioxide layer at the silicon interface followed by deposition of a metal layer, which is then diffused into the silicon dioxide. Preferred metals include zirconium and hafnium. A gate stack may be fabricated by adding a metal containing layer to an existing thermally grown SiO2 or a combination of SiO2, SiO3 and SiO4 (oxide-nitride or oxynitride) stacks.
83 citations
Authors
Showing all 7673 results
Name | H-index | Papers | Citations |
---|---|---|---|
David Blaauw | 87 | 750 | 29855 |
Krishnendu Chakrabarty | 79 | 996 | 27583 |
Rajesh Gupta | 78 | 936 | 24158 |
Philippe Renaud | 77 | 773 | 26868 |
Min Zhao | 71 | 547 | 24549 |
Gary L. Miller | 63 | 306 | 13010 |
Paul S. Ho | 60 | 475 | 13444 |
Ravi Subrahmanyan | 59 | 353 | 14244 |
Jing Shi | 53 | 222 | 10098 |
A. Alec Talin | 52 | 311 | 12981 |
Chi Hou Chan | 48 | 511 | 9504 |
Lin Shao | 48 | 380 | 12737 |
Johan Åkerman | 48 | 306 | 9814 |
Philip J. Tobin | 47 | 186 | 6502 |
Alexander A. Demkov | 47 | 331 | 7926 |