Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Method for forming interconnect bumps on a semiconductor die

Abstract: A method of forming an interconnect bump structure (32, 33). Under Bumb Metalization 11 (UBM) comprising a chrome layer (16), a copper layer (36), and a tin layer (40) is disclosed. In one embodiment, eutectic solder (45) is then formed over the UBM (11) and reflowed in order to form the interconnect bump stucture. In another embodement, a lead standoff (46) is formed over the UBM (11) before the formation of the eutectic solder (48).

Resource allocation in a communication system

Abstract: Methods and corresponding systems for determining a transmit power in a mobile device include receiving, in the mobile device, a cell-wide power control parameter related to a target receive power at a serving base station. Thereafter, a transmit power is calculated in response to the cell-wide power control parameter and an implicit mobile-specific power control parameter. The mobile device then transmits using the transmit power. The cell-wide power control parameter can be a cell target signal to interference-plus-noise ratio, or a fractional power control exponent. The implicit mobile-specific power control parameter can be a modulation and coding level previously used by the mobile device, or a downlink SINR level measured by the mobile device.

Process for forming dual metal gate structures

Abstract: A semiconductor device has a P channel gate stack comprising a first metal type and a second metal type over the first metal type and an N channel gate stack comprising the second metal type in direct contact with a gate dielectric/etch stop layer stack. The N channel gate stack and the P channel gate stack are etched by a dry etch. Either the gate dielectric or etch stop can be in contact with the substrate. The etch stop layer prevents the dry etch of the first and second metal layers from etching through the gate dielectric and gouging the underlying substrate.

Amorphous alloys for magnetic devices

Abstract: An amorphous layer of a cobalt iron-based (CoFe-based) magnetic alloy suitable for use in magnetoelectronic devices is disclosed. In the most preferred embodiments of the present invention, at least one amorphous layer is provided in an MTJ stack to increase the smoothness of the various layers in the MTJ stack while also enhancing the magnetic performance of the resulting device. Additionally, the alloys of the present invention are also useful in cladding applications to provide electrical flux containment for signal lines in magnetoelectronic devices and as a material for fabricating write heads.

High mobility NMOSFET structure with high-/spl kappa/ dielectric

Abstract: High-/spl kappa/ NMOSFET structures designed for enhancement mode operation have been fabricated with mobilities exceeding 6000 cm/sup 2//Vs. The NMOSFET structures which have been grown by molecular beam epitaxy on 3-in semi-insulating GaAs substrate comprise a 10 nm strained InGaAs channel layer and a high-/spl kappa/ dielectric layer (/spl kappa//spl cong/20). Electron mobilities of >6000 and 3822 cm/sup 2//Vs have been measured for sheet carrier concentrations n/sub s/ of 2-3/spl times/10/sup 12/ and /spl cong/5.85/spl times/10/sup 12/ cm/sup -2/, respectively. Sheet resistivities as low as 280 /spl Omega//sq. have been obtained.