Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Superimposed training for OFDM: a peak-to-average power ratio analysis

Abstract: Orthogonal frequency division multiplexing (OFDM) transmission with superimposed training is considered in this paper. One major disadvantage of OFDM is the significant amplitude fluctuations, i.e., high peak-to-average power ratios (PARs). High PARs require large backoff of the average operating power of a radio-frequency (RF) power amplifier (PA) in order to linearly amplify the signal, thus reducing the dc to RF power conversion efficiency. The PAR of the OFDM signal is examined with superimposed training, and its complementary cumulative distribution function (CCDF) is derived. Achievable lower and upper bounds on the CCDF are also determined. In addition, the PAR change is linked to the effective signal-to-noise ratio (SNR) and thus the bit-error-rate (BER) performance under the fixed dc power constraint. Simulation results are presented to illustrate the proposed PAR and power analysis for OFDM with superimposed training.

Electronic component assembly having an encapsulation material and method of forming the same

Abstract: An electronic component assembly (10) is formed by mounting an electronic component (31) to a substrate (11). An encapsulating material (33) is used to protect the electronic component (31) from environmental hazards. The encapsulating material (33) is formed by dispensing an encapsulating fluid over the electronic component (31). A trench (36) is formed in a masking layer (21) on a substrate (11) to stop the flow of the encapsulating fluid. The trench (36) provides an edge (35) which acts as a discontinuity in the surface (23) of the masking layer (21). This discontinuity is sufficient to control the flow of the encapsulating fluid until the encapsulating fluid is cured to form the encapsulating material (33).

Method and apparatus for stress relief in solder bump formation on a semiconductor device

Abstract: A semiconductor device (10) includes a bump structure that reduces stress and thus reduces passivation cracking and silicon cratering that can be a failure mode in semiconductor manufacturing. The stress is reduced by forming a polyimide layer (16) over a passivation layer (14). The polyimide layer (16) is extended beyond an edge of the passivation layer (14) over the metal pad (12). A solder bump (22) is composed of a eutectic material and is formed on the metal pad (12) and on the polyimide layer (16). The polyimide layer (16) prevents the solder bump (22) from contacting the passivation layer (14). This is useful for electroless or electroplating technology and may also be useful in other types of bump forming technology such as C4 and E3.

Reconfigurable systems using hybrid integrated circuits with optical ports

Abstract: A hybrid integrated circuit is provided that has a monocrystalline substrate such as silicon and a compound semiconductor layer such as gallium arsenide or indium phosphide An optical communications port may be formed on the hybrid integrated circuit Electrical equipment may be provided that includes electrical components At least a given one of the components may be a hybrid integrated circuit Data used for the operation of one of the given integrated circuit may be provided to the given integrated circuit through the optical communications port on that integrated circuit The data may be loaded rapidly in real time due to the wide bandwidth of the optical communications port

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

Abstract: The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects