Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Multiple step metallization process

Abstract: Metal step coverage is improved by utilizing a multiple step metallization process. In the first step, a thick portion of a metal layer is deposited on a semiconductor wafer at a cold temperature. The remaining amount of metal is deposited in a second step as the temperature is ramped up to allow for reflow of the metal layer through grain growth, recrystallization and bulk diffusion. The thick portion of the metal layer deposited at the cold temperature is of adequate thickness so that it remains continuous at the higher temperature and enhances via filling.

Stress–Strain Characteristics of Tin-Based Solder Alloys for Drop-Impact Modeling

Abstract: The stress–strain properties of eutectic Sn-Pb and lead-free solders at strain rates between 0.1 s−1 and 300 s−1 are required to support finite-element modeling of the solder joints during board-level mechanical shock and product-level drop-impact testing. However, there is very limited data in this range because this is beyond the limit of conventional mechanical testing and below the limit of the split Hopkinson pressure bar test method. In this paper, a specialized drop-weight test was developed and, together with a conventional mechanical tester, the true stress–strain properties of four solder alloys (63Sn-37Pb, Sn-1.0Ag-0.1Cu, Sn-3.5Ag, and Sn-3.0Ag-0.5Cu) were generated for strain rates in the range from 0.005 s−1 to 300 s−1. The sensitivity of the solders was found to be independent of strain level but to increase with increased strain rate. The Sn-3.5Ag and the Sn-3.0Ag-0.5Cu solders exhibited not only higher flow stress at relatively low strain rate but, compared to Sn-37Pb, both also exhibited higher rate sensitivity that contributes to the weakness of these two lead-free solder joints when subjected to drop impact loading.

Method and structure for reducing capacitance between interconnect lines

Abstract: A method and structure for reducing capacitance between interconnect lines (11, 24, 26) utilizes air gaps (17, 47) between the interconnect lines (11, 24, 26). Deposited over the interconnect lines (11, 24, 26), a silane oxide layer (14) forms a "breadloaf" shape which can be sputter etched to seal the air gaps (17, 47). Prior to the deposition of the sputter etched silane oxide layer (14), spacers (13, 42, 43) can be formed around the interconnect lines (11, 24, 26) to increase the aspect ratio of gaps (23, 31) between the interconnect lines (11, 24, 26) which facilitates the formation of the "breadloaf" shape of the silane oxide layer (14).

Acoustically regulated polishing process

Abstract: A chemical-mechanical-polishing process in which acoustic waves are generated in the polishing slurry (18) to enable detection of an end-point in the polishing process, and to continuously clean the surface of a polishing pad (14) in a polishing apparatus (10). Acoustic waves are generated in the polishing slurry (18) by submerging a transducer (28) in the polishing slurry (18). The transducer (28) is powered by a voltage amplifier (30) coupled to a frequency generator (32). The frequency of the acoustic waves is adjusted by the frequency generator (32) to obtain optimum wave generation in the polishing slurry (18). The end-point of the polishing process is detected by a change in the acoustic wave velocity in the polishing slurry (18), which occurs when the slurry composition changes at end-point. The wave velocity is monitored by a receiver (34) submerged in the polishing slurry (18) at a predetermined distance from the transducer (28). Additionally, the acoustic wave frequency can be adjusted by the frequency generator (32) to induce sonic vibration in the polishing pad (14) such that continuous cleaning action is attained on the surface of the polishing pad (14).

Method for underencapsulating components on circuit supporting substrates

Abstract: A method and apparatus for underencapsulating a component (502) on a substrate (402). The method robotically places an underencapsulant film (406) on at least one surface of a first surface of the component (502) and a second surface of a substrate (402), the first and second surfaces substantially opposing each other when the component (502) is placed on the substrate (402). Next, the method places the component (502) on the substrate (402) to dispose the underencapsulant film (406) between the first and second surfaces. The method then bonds (1006,1008 or 1006,1010) the component (502) to the substrate (402) with the underencapsulant (406).