Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Apparatus and method for varying the coupling of a radio frequency signal

Abstract: An apparatus and method for varying coupling of a radio frequency (RF) signal (408). This is advantageously used for increasing the dynamic range of a power detector (406) in an automatic power level control loop (403) of a transmission unit (404), while maintaining transmission unit efficiency at higher power levels. This is accomplished by selecting between a first operating mode of the RF coupler (405) having strong coupling, responsive to a first predetermined power level, such that the RF coupler (405) produces a first coupled RF signal (509) responsive to the RF signal (408) and a second operating mode of the RF coupler (405) having weak coupling, responsive to a second predetermined power level, such that the RF coupler (405) produces a second coupled RF signal (510) responsive to the RF signal (408).

Led driver with segmented dynamic headroom control

Abstract: Techniques for dynamic headroom control in a light emitting diode (LED) system are disclosed. An output voltage is provided to drive a plurality of LED strings. A feedback controller monitors the tail voltages of the LED strings to identify the minimum tail voltage and adjusts the output voltage based on the lowest tail voltage. The LED strings grouped into subsets and the feedback controller is segmented such that, for a certain duration, a minimum tail voltage is determined for each subset. The minimum tail voltages of the subsets are used to determine the overall minimum tail voltage of the plurality of LED strings for the certain duration so as to control the output voltage in the following duration. The segments of the feedback controller can be implemented in separate integrated circuit (IC) packages, thereby facilitating adaptation to different numbers of LED strings by integrating the corresponding number of IC packages.

Stackable molded packages and methods of making the same

Abstract: A first packaged integrated circuit (IC) includes a package substrate, at least one IC die attached to a first surface of the package substrate, a plurality of conductive members on the first surface at least partially surrounding the at least one IC die and electrically connected to the at least one IC die, an encapsulant over the first surface surrounding the at least one IC die and the plurality of conductive members, wherein at least a portion of each of the plurality of conductive members is exposed by the encapsulant. A second packaged IC may be stacked onto the first packaged IC. The second packaged IC includes at least one IC die and a plurality of conductive members, each conductive member of the plurality of conductive members of the second packaged IC is in contact with a corresponding conductive member of the plurality conductive members of the first packaged IC.

Pipelined dual port integrated circuit memory

Abstract: A pipelined dual port integrated circuit memory (20) includes an array (30) of static random access memory (SRAM) cells, where each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). A control circuit (32) controls access to the memory cells, where substantially simultaneous requests for access are serviced sequentially within a single cycle of a clock signal of a data processor that is accessing the memory (20). An address collision detector (110) compares addresses provided to the two ports, and generates a match signal that is used for determining which of the two ports are serviced first, independent of which port is read from, or written to. Because dual port functionality is obtained using a single port SRAM array (30), the memory (20) may be manufactured using relatively less integrated circuit surface area, and therefore at a lower cost.

Magnetic device having multi-layer with insulating and conductive layers

Abstract: A magnetic device (40) having multi-layer (41-45) with insulating layer (45) and conductive layer (42). The conductive layer (42) is positioned between a first magnetic layer (41) and a third magnetic layer (44). The insulating layer (45) is positioned between a second magnetic layer (43) and the third magnetic layer (44), and which forms a tunnel junction between the second and third layers. Magnetic vectors in the first magnetic layer (41) magnetically couple with ones in the second magnetic layer (43) so that the magnetic coupling loop formed around the third magnetic layer (44) allows magnetic vectors in the third magnetic layer (44) to be switchable in a low magnetic field. Consequently, total power consumption of the magnetic device (60) decreases.