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Institution

Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..


Papers
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Patent
31 Aug 2005
TL;DR: In this article, the authors describe a semiconductor device that is formed by positioning a gate overlying a silicon layer of the semiconductor, where a thermal process diffuses the stressor material into the silicon layer.
Abstract: A semiconductor device (10) is formed by positioning a gate (22) overlying a semiconductor layer (16) of preferably silicon. A semiconductor material (26) of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel (17) in which a stressor material layer (30) is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

67 citations

Patent
05 Apr 1999
TL;DR: In this article, a conductive barrier layer overlies a portion of the interconnect, a passivation layer (92 ) overlies the conductive barriers, and the passivation has an opening that exposes portions of the barrier layer.
Abstract: An interconnect overlies a semiconductor device substrate ( 10 ). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer ( 92 ) overlies the conductive barrier layer and the passivation layer ( 92 ) has an opening that exposes portions of the conductive barrier layer ( 82 ). In an alternate embodiment a passivation layer ( 22 ) overlies the interconnect, the passivation layer ( 22 ) has an opening ( 24 ) that exposes the interconnect and a conductive barrier layer ( 32 ) overlies the interconnect within the opening ( 24 ).

67 citations

Patent
15 Feb 2002
TL;DR: In this article, an apparatus and method for separating a semiconductor die (303) from an adhesive tape (32) is presented. But the method is not suitable for the removal of the die.
Abstract: An apparatus and method for separating a semiconductor die (303) from an adhesive tape (32) are disclosed. The apparatus includes a blade (34) mechanically coupled to a blade holder (36), wherein the blade (34) is inclined relative to the primary surface of the semiconductor die (303). The method further comprises lifting the semiconductor die (303) while it is attached to the adhesive tape (32) to assist disengagement. The blade (34) facilitates peeling of the semiconductor die (303) from the adhesive tape (32) while distributing stress exerted on the semiconductor die (303) over a larger surface area resulting in reduced die fractures (20).

67 citations

Journal ArticleDOI
TL;DR: The suggested architecture provides an enhanced security protection scheme for use in smartphones, PDA's, as well as other similar systems, and sensitive data storage facilities, cryptographic engines, and physical protection mechanisms are presented and described in detail.

67 citations

Patent
29 Sep 1994
TL;DR: In this article, an electronic assembly is fabricated by reflow heating of a first, less compliant solder paste and a compliant preform, so as to cause compliant material of the preform to dissolve into the solder paste.
Abstract: An electronic assembly (100) includes multiple solder connections (101) coupling faying surfaces (202, 204) of two substrates (106, 108). A solder connection (201) is fabricated by reflow heating of a first, less compliant solder paste (312, 314) and a compliant preform (210) so as to cause compliant material of the preform (210) to dissolve into the solder paste (312, 314). Upon solidification of the solder paste (312, 314), blended regions (520, 522), having a gradual, changing concentration of compliant material form between resulting fillets (212, 214) and the preform (210). The blended regions (520, 522) transfer temperature induced shear stresses, caused by thermal cycling of the electronic assembly (100), from the fillets (212, 214) into the compliant preform (210).

67 citations


Authors

Showing all 7673 results

NameH-indexPapersCitations
David Blaauw8775029855
Krishnendu Chakrabarty7999627583
Rajesh Gupta7893624158
Philippe Renaud7777326868
Min Zhao7154724549
Gary L. Miller6330613010
Paul S. Ho6047513444
Ravi Subrahmanyan5935314244
Jing Shi5322210098
A. Alec Talin5231112981
Chi Hou Chan485119504
Lin Shao4838012737
Johan Åkerman483069814
Philip J. Tobin471866502
Alexander A. Demkov473317926
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20211
20203
201910
201826
201779
2016267