Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics

Abstract: In a magnetoresistive random access memory (MRAM), a magnetic tunnel junction (MTJ) (54) cell is stacked with an asymmetric tunnel device (56). This device, when used in a crosspoint MRAM array, improves the sensing of the state or resistance of the MTJ cells. Each MTJ cell has at least two ferromagnetic layers (42, 46) separated by an insulator (44). The asymmetric tunnel device (56) is electrically connected in series with the MTJ cell and is formed by at least two conductive layers (48, 52) separated by an insulator (50). The asymmetric tunnel device may be a MIM (56), MIMIM (80) or a MIIM (70). Asymmetry results from conducting electrons in a forward biased direction at a significantly greater rate than in a reversed biased direction. Materials chosen for the asymmetric tunnel device are selected to obtain an appropriate electron tunneling barrier shape to obtain the desired rectifying current/voltage characteristic.

On chip network

Abstract: An OCN for integrated processing elements including a network with multiple ports and multiple port interfaces. The ports and the port interfaces conform to a consistent port protocol. Each port interface converts information between bus transactions of a corresponding processing element and network packets and exchanges network packets with other port interfaces. Each port includes an arbitration interface and a data interface and the network includes an interconnect and an arbiter. The interconnect includes selectable data paths between the ports for packet datum transfer. A port source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. A port destination interface receives packet datums via available input buffers. Each transaction request includes a transaction size and a destination port address. The arbiter receives transaction requests, arbitrates among transaction requests, provides acknowledgements and controls the interconnect to select data paths between sources and destinations.

Radio frequency circuit with integrated on-chip radio frequency signal coupler

Abstract: A radio frequency ('RF') (100) circuit configured in accordance with an embodiment of the invention is fabricated on a substrate using integrated passive device ('IPD') process technology. The RF circuit (100) (which may be, for example, a harmonic filter) includes at least one RF signal line section (204) and an integrated RF coupler (304) located proximate to the RF signal line section. The integrated RF coupler (304), its output (212) and grounding contact pads (210), and its matching network (208) are fabricated on the same substrate using the same IPD process technology. The integrated RF coupler provides efficient and reproducible RF coupling without increasing the die footprint of the RF circuit.

Integrated circuit comprising frequency generation circuitry for controlling a frequency source

Abstract: An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal

32nm general purpose bulk CMOS technology for high performance applications at low voltage

Abstract: This paper presents for the first time a full 32 nm CMOS technology for high data rate and low operating power applications using a conventional high-k with single metal gate stack. High speed digital transistors are demonstrated 22% delay reduction for ring oscillator (RO) at same power versus previous SiON technology. Significant matching factor (AVT) improvement (AVT~2.8 mV.um) and low 1/f noise aligned with poly SiON are reported. Excellent static noise margin (SNM) of 213 mV has been achieved at low voltage for a high density 0.157 um2 SRAM cell. Hierarchical BEOL based on extreme low k (ELK) dielectric (k~2.4) is presented allowing high density wiring with low RC delay. Reliability criteria have been met for hot carrier injection (HCI), gate dielectric break-down (TDDB) and bias temperature instability (BTI) extracted at 125degC.