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Institution

Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..


Papers
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Patent
19 Mar 2004
TL;DR: In this paper, an algorithmic or cyclic data converter using an RSD stage having a switched capacitor network for efficiently scaling at least one externally supplied reference voltage is described. But the RSD A/D converter is not designed to scale the reference voltage by any scaling factor.
Abstract: An algorithmic or cyclic data converter uses an RSD stage having a switched capacitor network for efficiently scaling at least one externally supplied reference voltage. A reference voltage is scaled by using capacitor ratios that also function to provide an output voltage used as a residue output of the RSD A/D converter. The residue is used to generate a bit value corresponding to the magnitude of the residue. Two RSD stages cycle back and forth generating a logic value each half clock cycle until the desired bit resolution is achieved. In one form, the RSD stage scales the externally supplied reference voltage only by factors of less than one. In another form, the RSD stage scales the reference voltage by any scaling factor. A reference voltage scaling circuit separate from the RSD stage is avoided.

65 citations

Patent
08 Oct 2003
TL;DR: In this article, a method for transmitting data packets from a source device in a wireless network is described, where the source device receives a channel time allocation identifying the source devices as assigned to transmit and a destination device as assigning to listen during the channel-time allocation.
Abstract: A method is provided for transmitting data packets from a source device in a wireless network The source device receives a channel time allocation identifying the source device as assigned to transmit and a destination device as assigned to listen during the channel time allocation If the source device has any primary data to send to the destination device, it will do so during the channel time allocation If time remains in the channel time allocation once the primary data (if any) has been sent to the destination device, the source device will determine whether it has any secondary data to send to a secondary device If so, the source device will determine whether the secondary device will be listening during the channel time allocation If the secondary device will be listening, the source device then sends the secondary data to the secondary device during the channel time allocation

65 citations

Patent
24 Jul 2002
TL;DR: In this article, the authors present a method for prioritizing requests in a data processor (12) having a bus interface unit (32), which includes receiving a first request from a first bus requesting resource (e.g. 30) and a second request from an instruction prefetch buffer (i.e. 28), and using a threshold corresponding to the first or second bus requesting resources to prioritize the first and second requests.
Abstract: The present invention relates generally to data processors and more specifically, to data processors having an adaptive priority controller. One embodiment relates to a method for prioritizing requests in a data processor (12) having a bus interface unit (32). The method includes receiving a first request from a first bus requesting resource (e.g. 30) and a second request from a second bus requesting resource (e.g. 28), and using a threshold corresponding to the first or second bus requesting resource to prioritize the first and second requests. The first and second bus requesting resources may be a push buffer (28) for a cache, a write buffer (30), or an instruction prefetch buffer (24). According to one embodiment, the bus interface unit (32) includes a priority controller (34) that receives the first and second requests, assigns the priority, and stores the threshold in a threshold register (66). The priority controller (34) may also include one or more threshold registers (66), subthreshold registers (68), and control registers (70).

65 citations

Patent
29 Aug 2002
TL;DR: A data storage system having a non-IC based memory and an IC based non-volatile memory for storing user data is discussed in this article, where the IC-based memory is utilized to store user data from an information device in order to increase the speed and/or the effective storage capacity of the system.
Abstract: A data storage system having a non IC based memory and an IC based non-volatile memory for storing user data. In one example, the IC based non-volatile memory is implemented with MRAM. Examples of non IC based memory include e.g. hard disks, tape, and compact disks. In some examples, the IC based memory is utilized to store user data from an information device in order to increase the speed and/or the effective storage capacity of the data storage system. In some examples, a portion of a standard size block of user data can be stored on spaces of the non IC based memory that are deficient for storing a standard size block with the remaining portion being stored in IC based memory. Portions of a file of user data may be non-volatilely stored in the IC based memory in order to more quickly provide the file to an information device. For example, data of a file, that if stored in a location on the non IC based media would significantly increase the retrieval time of the file, can be stored in the IC based media.

65 citations

Patent
25 Jun 2002
TL;DR: In this paper, a method for fabricating an RF enhancement mode FET having improved gate properties is provided, which comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, creating (105) an implant region
Abstract: A method for fabricating an RF enhancement mode FET (30) having improved gate properties is provided. The method comprises the steps of providing (131) a substrate (31) having a stack of semiconductor layers (32-35) formed thereon, the stack including a cap layer (35) and a central layer (33) defining a device channel, forming (103) a photoresist pattern (58) over the cap layer, thereby defining a masked region and an unmasked region, and, in any order, (a) creating (105) an implant region (36, 37) in the unmasked region, and (b) removing (107) the cap layer from the unmasked region. By forming the implant region and cap region with no overlap, a device with low current leakage may be achieved.

65 citations


Authors

Showing all 7673 results

NameH-indexPapersCitations
David Blaauw8775029855
Krishnendu Chakrabarty7999627583
Rajesh Gupta7893624158
Philippe Renaud7777326868
Min Zhao7154724549
Gary L. Miller6330613010
Paul S. Ho6047513444
Ravi Subrahmanyan5935314244
Jing Shi5322210098
A. Alec Talin5231112981
Chi Hou Chan485119504
Lin Shao4838012737
Johan Åkerman483069814
Philip J. Tobin471866502
Alexander A. Demkov473317926
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20211
20203
201910
201826
201779
2016267