Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Closed loop power control with high dynamic range

Abstract: A method (500) and apparatus (300, 400, 601) facilitate closed loop transmit power control in a power control loop at and during a transition from one transmit power level to another transmit power level in a transmitter. The apparatus includes a reference path (326) configured to provide a reference signal (325) and a gain compensation signal (417), a detect path (327) configured to process, in accordance with the gain compensation signal, a detected signal corresponding to a power level to provide a gain compensated detected signal; and a power control path (328) configured to generate a power control value in accordance with the reference signal, the gain compensated detected signal, and a loop compensation factor associated with the gain compensation signal where the power control value is suitable for setting the power level for the transmission.

High bandwidth cache-to-processing unit communication in a multiple processor/cache system

Abstract: A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set.

Method for testing integrated devices

Abstract: An integrated device test system (10, 40) having AC and DC measurement modes of operation comprises a drive circuit (11, 41), a programmable measurement unit (12) and a switch (18). The drive circuit (11, 41) may be a current mode drive circuit (11) or a voltage mode drive circuit (41). The drive circuit (11, 41) is coupled to the programmable measurement unit (12) and a device under test (64). In a DC mode of operation, the switch (18) is configured to couple a sense terminal (39) with one end of an isolation resistor (66). A second end of the isolation resistor (66) is connected to a pin (63) of the device under test (64). In an AC mode of operation, the switch (18) is configured to couple the sense terminal (39) with the drive circuit (11, 41) and the force terminal (35) of the programmable measurement unit (12).

Apparatus for reducing power consumed by a static microprocessor

Abstract: In response to a software instruction, a static microprocessor is placed in a low current mode by disabling clock pulse generation. Means are provided for disabling a master oscillator when a STOP instruction is decoded. Additional means are provided for inhibiting clock pulses when a WAIT instruction is decoded without disabling the master oscillator. Clock pulse generation is again enabled upon receipt of a reset or interrupt signal.

Multilayered through via

Abstract: A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV.