Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

A Statistical Traffic Model for On-Chip Interconnection Networks

Abstract: Network traffic modeling is a critical first step towards understanding and unraveling network power/performancerelated issues. Extensive prior research in the area of classic networks such as the Internet, Ethernet, and wireless LANs transporting TCP/IP, HTTP, and FTP traffic among others, has demonstrated how traffic models and model-based synthetic traffic generators can facilitate understanding of traffic characteristics and drive early-stage simulation to explore a large network design space. Though on-chip networks (a.k.a networks-on-chip (NoCs)) are becoming the de-facto scalable communication fabric in many-core systems-on-a-chip (SoCs) and chip multiprocessors (CMPs), no on-chip network traffic model that captures both spatial and temporal variations of traffic has been demonstrated yet. As available on-chip resources increase with technology scaling, enabling a myriad of new network architectures, NoCs need to be designed from the application’s perspective. In this paper we propose such an empirically-derived network on-chip traffic model for homogeneous NoCs. Our comprehensive model is based on three statistical parameters described with a 3-tuple, and captures the spatio-temporal characteristics of NoC traffic accurately with less than 5% error when compared to actual NoC application traces gathered from fullsystem simulations of three different chip platforms. We illustrate two potential uses of our traffic model: how it allows us to characterize and gain insights on NoC traffic patterns, and how it can be used to generate synthetic traffic traces that can drive NoC design-space exploration.

Enhancement-Mode GaAs MOSFETs With an $\hbox{In}_{0.3} \hbox{Ga}_{0.7}\hbox{As}$ Channel, a Mobility of Over 5000 $ \hbox{cm}^{2}/\hbox{V} \cdot \hbox{s}$ , and Transconductance of Over 475 $\mu\hbox{S}/\mu\hbox{m}$

Abstract: We present metal-gate high-k-dielectric enhancement-mode (e-mode) III-V MOSFETs with the highest reported effective mobility and transconductance to date. The devices employ a GaGdO high-k (k = 20) gate stack, a Pt gate, and a delta-doped InGaAs/AlGaAs/GaAs hetero-structure. Typical 1-mum gate length device figures of merit are given as follows: saturation drive current, Id,sat = 407 muA/mum; threshold voltage, Vt = +0.26 V; maximum extrinsic transconductance, gm = 477 muS/mum (the highest reported to date for a III-V MOSFET); gate leakage current, Ig = 30 pA; subthreshold swing, S = 102 mV/dec; on resistance, Ron = 1920 Omega-mum; Ion/Ioff ratio = 6.3 x 104; and output conductance, gd = 11 mS/mm. A peak electron mobility of 5230 cm2/V. s was extracted from low-drain-bias measurements of 20 mum long-channel devices, which, to the authors' best knowledge, is the highest mobility extracted from any e-mode MOSFET. These transport and device data are highly encouraging for future high-performance n-channel complementary metal-oxide-semiconductor solutions based on III-V MOSFETs.

UV cure process and tool for low k film formation

Abstract: A process and system for forming a low dielectric film in a semiconductor fabrication process are disclosed. Initially, a carbon-doped silicon oxide film is deposited on a semiconductor wafer. Light energy, such as ultraviolet (UV) energy, is then applied to the deposited film to cure the film. In one embodiment, at least 30% of the light energy is at a frequency greater than that of visible light. In the preferred embodiment, the application of the light energy to the wafer does not significantly heat the wafer. The invention further contemplates a cluster tool or system suitable for forming and curing the dielectric film. The cluster tool includes a first chamber coupled to an organosilane source, a second chamber configured to apply light energy to a wafer received in the second chamber, and a robotic section suitable for controlling movement of wafers between the first chamber and the second chamber.

Method and system for enabling device functions based on distance information

Abstract: A method, device and computer readable medium for enabling and blocking communications with a remote device based on a distance of the remote device. The method on which the device and computer readable medium are based includes transmitting a message from a local device to a remote device via an ultra wide band (UWB) wireless medium and receiving a response from the remote device via the UWB wireless medium. The transmitting and receiving steps are preferably performed in accordance with a Media Access Control (MAC) protocol. A distance between the local device and the remote device is then determined based on a time between the transmitting of the message and the receiving of the response and a function, such as communicating with the remote device, is performed in the local device based on the distance determined. The communication between the local device and the remote device may be enabled or disabled depending on the distance that the remote device is from the local device. In addition, the distance information for a remote device may be continually updated, or updated only if communication to the remote device are blocked. A positional map may be generated based on distance data determined for a plurality of reference points and the user may select the remote device from the positional map to enable communications to the positional map.

Digital communications processor

Abstract: An integrated circuit ( 203 ) for use in processing streams of data generally and streams of packets in particular. The integrated circuit ( 203 ) includes a number of packet processors ( 307, 313, 303 ), a table look up engine ( 301 ), a queue management engine ( 305 ) and a buffer management engine ( 315 ). The packet processors ( 307, 313, 303 ) include a receive processor ( 421 ), a transmit processor ( 427 ) and a risc core processor ( 401 ), all of which are programmable. The receive processor ( 421 ) and the core processor ( 401 ) cooperate to receive and route packets being received and the core processor ( 401 ) and the transmit processor ( 427 ) cooperate to transmit packets. Routing is done by using information from the table look up engine ( 301 ) to determine a queue ( 215 ) in the queue management engine ( 305 ) which is to receive a descriptor ( 217 ) describing the received packet's payload.