Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Semiconductor device having an insertable heat sink and method for mounting the same

Abstract: A semiconductor device is disclosed having an electronic component mounted to a mounting surface opposite a heat transfer surface of a die support member. The electronic component includes a plurality of bonding pads each electrically coupled to a plurality of package leads by a number of inner leads. A package body encloses the electronic component, the inner leads, the proximal ends of the package leads and the mounting surface of the die support member. The package body includes an opening exposing a portion of the heat transfer surface of the die support member. An insertable thermally conductive heat sink extends into the opening in the package body making thermal contact with the heat transfer surface of the die support member. A thermally conductive electrically insulating adhesive joins the heat sink to the package body securing the heat sink to the package body. In the assembly process, the package body is formed prior to attachment of the heat sink. During the process of soldering the package leads of the semiconductor device to a mounting substrate, gasses within the package body can escape through the opening before excessive pressure buildup occurs within the package body.

Method and apparatus for generating a pulse width modulated signal

Abstract: A method and apparatus for a pulse width modulated (PWM) signal (30, 130) is provided. The input is a digital signal which is a modulated signal (24, 124). In the illustrated form, the modulated input signal is either a PDM signal or a PCM signal. In one embodiment of the present invention a PCM to PWM converter (16, 116) includes correction of duty ratio circuitry (48). The methodology used may include recursion on the values obtained after prediction, interpolation, and correction. The digital to analog conversion system (10) uses a PDM to PWM converter (20) which operates in an all digital domain and includes no analog circuitry.

Rule based floorplanner

Abstract: A rule based floorplanner for a macrocell array having a plurality of predetermined macrocells. The floorplanner uses a net list (23), a macrocell list (26), and a list of design constraints (31) and characteristics of the base array itself to derive an initial Burain score. A trial floorplan is attempted (33) and checked against a list of theoretical rules (39) and a list of empirical rules (38) to determine a measured Burain score (36) which accurately indicates the difficulty which can be expected when completing the design.

Process for producing and inspecting a lithographic reticle and fabricating semiconductor devices using same

Abstract: A process for fabricating a semiconductor device includes the formation of a lithographic reticle (20) having a lithographic pattern (18) overlying a reticle substrate (10). In one embodiment, a reticle inspection database incorporates altered resolution assisting features (30,32) to inspect the lithographic pattern (18). The dimensional difference between the reticle inspection database and the lithographic reticle is substantially equal to the process bias realized during reticle fabrication. Inspection of the lithographic reticle (20) using a reticle inspection database containing altered resolution assisting features reduces the false detection of defects and provides increased sensitivity in the reticle inspection process.

Packaging an integrated circuit die with backside metallization

Abstract: A method ( 32 ) of packaging integrated circuit (IC) dies ( 48 ) includes applying ( 36 ) a laminating material ( 44 ) to a wafer ( 40 ), and separating ( 46 ) the wafer ( 40 ) into multiple IC dies ( 48 ) such that the laminating material ( 44 ) is applied to back surfaces ( 52 ) of the IC dies ( 48 ). Each of the IC dies ( 48 ) is positioned ( 62 ) with an active surface ( 50 ) facing a support substrate ( 56 ). An encapsulant layer ( 72 ) is formed ( 64 ) overlying the laminating material ( 44 ) and the back surfaces ( 52 ) of the IC dies ( 48 ) from a molding compound ( 66 ). The molding compound ( 66 ) and the laminating material ( 44 ) are removed from the back surfaces ( 52 ) of the IC dies ( 48 ) to form ( 76 ) openings ( 78 ) exposing the back surfaces ( 52 ). Conductive material ( 84, 88 ) is placed in the openings ( 78 ) and functions as a heat sink and/or a ground for the IC dies ( 48 ).